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MC68HC05E0/D
MC68HC05E0 TECHNICAL DATA
HC05
MC68HC05E0
TECHNICAL DATA
INTRODUCTION FUNCTIONAL PIN DESCRIPTION CPU CORE AND INSTRUCTION SET RESETS, INTERRUPTS AND LOW POWER MODES MEMORY AND ADDRESSING PARALLEL INPUT/OUTPUT PORTS TIMERS SERIAL INTERFACE ELECTRICAL SPECIFICATIONS MECHANICAL DATA ORDERING INFORMATION
1 2 3 4 5 6 7 8 9 10 11
1 2 3 4 5 6 7 8 9 10 11
INTRODUCTION FUNCTIONAL PIN DESCRIPTION CPU CORE AND INSTRUCTION SET RESETS, INTERRUPTS AND LOW POWER MODES MEMORY AND ADDRESSING PARALLEL INPUT/OUTPUT PORTS TIMERS SERIAL INTERFACE ELECTRICAL SPECIFICATIONS MECHANICAL DATA ORDERING INFORMATION
MC68HC05E0
High-density complementary metal oxide semiconductor (HCMOS) microcontroller unit
All Trade Marks recognized. This document contains information on new products. Specifications and information herein are subject to change without notice.
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Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters can and do vary in different applications. All operating parameters, including "Typicals", must be validated for each customer application by customer's technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer. The Customer should ensure that it has the most up to date version of the document by contacting its local Motorola office. This document supersedes any earlier documentation relating to the products referred to herein. The information contained in this document is current at the date of publication. It may subsequently be updated, revised or withdrawn.
(c) MOTOROLA LTD., 1996
Conventions
Where abbreviations are used in the text, an explanation can be found in the glossary, at the back of this manual. Register and bit mnemonics are defined in the paragraphs describing them. An overbar is used to designate an active-low signal, eg: RESET. Unless otherwise stated, shaded cells in a register diagram indicate that the bit is either unused or reserved; `u' is used to indicate an undefined state (on reset).
TABLE OF CONTENTS
Paragraph Number TITLE Page Number
1 INTRODUCTION
1.1 1.2 General ..................................................................................................................1-1 Features.................................................................................................................1-1
2 FUNCTIONAL PIN DESCRIPTION
2.1 2.2 2.2.1 2.2.2 2.2.3 2.3 2.4 2.5 2.6 2.7 2.8 2.9 2.10 2.11 2.12 2.13 2.14 VDD and VSS ........................................................................................................2-1 OSC1/OSC2 ..........................................................................................................2-1 Crystal..............................................................................................................2-1 Ceramic Resonator ..........................................................................................2-1 External Clock..................................................................................................2-2 RESET...................................................................................................................2-2 Port A (PA0 - PA7) .................................................................................................2-2 Port B (PB0 - PB7).................................................................................................2-2 Port C (PC0 - PC7) ................................................................................................2-2 Port D (PD0 - PD7) ................................................................................................2-4 Port E (PE0 - PE3).................................................................................................2-4 CSROM .................................................................................................................2-4 INTX ......................................................................................................................2-5 TS ..........................................................................................................................2-5 TEST .....................................................................................................................2-5 Expanded Address Bus (A0 - A12) .......................................................................2-5 External Data Bus (D0 - D7) .................................................................................2-5
3 CPU CORE AND INSTRUCTION SET
3.1 Registers ...............................................................................................................3-1 3.1.1 Accumulator (A) ...............................................................................................3-1 3.1.2 Index register (X)..............................................................................................3-2 3.1.3 Program counter (PC) ......................................................................................3-2
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3.1.4 Stack pointer (SP)............................................................................................3-2 3.1.5 Condition code register (CCR).........................................................................3-2 3.2 Instruction set ........................................................................................................3-3 3.2.1 Register/memory Instructions ..........................................................................3-4 3.2.2 Branch instructions ..........................................................................................3-4 3.2.3 Bit manipulation instructions ............................................................................3-4 3.2.4 Read/modify/write instructions.........................................................................3-4 3.2.5 Control instructions ..........................................................................................3-4 3.2.6 Tables...............................................................................................................3-4 3.3 Addressing modes.................................................................................................3-11 3.3.1 Inherent............................................................................................................3-11 3.3.2 Immediate ........................................................................................................3-11 3.3.3 Direct ...............................................................................................................3-11 3.3.4 Extended..........................................................................................................3-12 3.3.5 Indexed, no offset ............................................................................................3-12 3.3.6 Indexed, 8-bit offset .........................................................................................3-12 3.3.7 Indexed, 16-bit offset .......................................................................................3-12 3.3.8 Relative ............................................................................................................3-13 3.3.9 Bit set/clear ......................................................................................................3-13 3.3.10 Bit test and branch...........................................................................................3-13
4 RESETS, INTERRUPTS AND LOW POWER MODES
4.1 Resets ...................................................................................................................4-1 4.1.1 Power-on Reset ...............................................................................................4-2 4.1.2 RESET Pin.......................................................................................................4-2 4.2 Interrupts ...............................................................................................................4-2 4.2.1 Hardware Controlled Interrupt Sequence ........................................................4-4 4.2.2 Non-Maskable Software interrupt (SWI) ..........................................................4-7 4.2.3 Maskable Hardware Interrupts.........................................................................4-7 4.2.3.1 External Interrupt (INTX)............................................................................4-7 4.2.3.2 Real Time Interrupt ....................................................................................4-7 4.2.3.3 Port C Wake-up ..........................................................................................4-7 4.2.3.4 Timer A Interrupt ........................................................................................4-8 4.2.3.5 Timer B Interrupt ........................................................................................4-8 4.2.3.6 SI Interrupt .................................................................................................4-8 4.2.4 Interrupt Control...............................................................................................4-8 4.3 Low Power Modes .................................................................................................4-10 4.3.1 STOP ...............................................................................................................4-10 4.3.2 WAIT ................................................................................................................4-10
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5 MEMORY AND ADDRESSING
5.1 5.2 5.3 5.4 5.5 5.6 Memory Map..........................................................................................................5-1 RAM.......................................................................................................................5-1 ROM ......................................................................................................................5-2 Registers ...............................................................................................................5-2 Vectors...................................................................................................................5-2 Address Decoding and System Expansion ...........................................................5-2
6 PARALLEL INPUT/OUTPUT PORTS
6.1 6.2 6.3 6.4 6.5 Bidirectional Ports..................................................................................................6-1 Port C Wake-up Function.......................................................................................6-3 Port D Alternate Functions ....................................................................................6-4 Serial Interface Support Functions on Port E ........................................................6-6 Other Port Considerations .....................................................................................6-7
7 TIMERS
7.1 7.2 7.3 7.4 7.5 Sub-system Clock Control .....................................................................................7-1 Timer A ..................................................................................................................7-2 Timer B ..................................................................................................................7-3 Control Registers for Timer A and Timer B ............................................................7-4 Real Time Interrupt Timer ......................................................................................7-5
8 SERIAL INTERFACE
8.1 8.2 8.3 8.4 General ..................................................................................................................8-1 SPI Configuration...................................................................................................8-3 I2C-Bus Configuration ...........................................................................................8-6 Transmission Error Detection.................................................................................8-10
9 ELECTRICAL SPECIFICATIONS
9.1 9.2 9.3 Introduction ............................................................................................................9-1 Maximum Ratings ..................................................................................................9-1 Thermal Characteristics and Power Considerations..............................................9-2
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Paragraph Number 9.4 9.5 9.6
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DC Electrical Characteristics.................................................................................9-3 AC Electrical Characteristics .................................................................................9-4 Serial Interface Timing...........................................................................................9-7
10 MECHANICAL DATA
10.1 68-pin PLCC Package .........................................................................................10-1
11 ORDERING INFORMATION
11.1 11.2 11.3 EPROMs..............................................................................................................11-1 Verification media ................................................................................................11-1 ROM Verification Units (RVUs) ............................................................................11-1
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LIST OF FIGURES
Figure Number 1-1 2-1 3-1 3-2 4-1 4-2 4-3 4-4 5-1 5-2 5-3 6-1 6-2 6-3 6-4 6-5 7-1 7-2 7-3 7-4 8-1 8-2 8-3 8-4 9-1 9-2 9-3 9-4 9-5 10-1 TITLE Page Number
Functional Block Diagram.......................................................................................1-2 Oscillator Connections............................................................................................2-3 Programming model ...............................................................................................3-1 Stacking order ........................................................................................................3-2 Power-on Reset and RESET ..................................................................................4-1 Internal Processor Interrupt Signal IRQB ...............................................................4-3 Hardware Interrupt Flow Chart ...............................................................................4-5 STOP/WAIT Flow Chart..........................................................................................4-6 Minimum System with External Memory ................................................................5-4 More Complex Expanded System ..........................................................................5-4 Memory map of the MC68HC05E0 ........................................................................5-6 Bidirectional I/O Port Structure ...............................................................................6-2 Port C Wake-up Function........................................................................................6-4 Port D Structure......................................................................................................6-6 Port E Structure ......................................................................................................6-7 Port Logic Levels ...................................................................................................6-8 Sub-system Clock Generation ................................................................................7-1 Timer A Structure ...................................................................................................7-2 Timer B Structure ...................................................................................................7-3 Real Time Interrupt Timer Structure .......................................................................7-5 Serial Port Baud Rate Generation ..........................................................................8-2 SPI Data/Clock Relationship ..................................................................................8-3 I2C-bus Data/Clock Relationship............................................................................8-7 Serial Interface Transmission Error Detection ........................................................8-10 Equivalent Test Load ..............................................................................................9-2 Stop Recovery Timing Diagram..............................................................................9-5 Expanded Bus Timing Diagram ..............................................................................9-6 SPI Timing Diagram................................................................................................9-7 I2C-bus Timing Diagram ........................................................................................9-7 Pinout for 68-pin PLCC (Plastic Leadless Chip Carrier).......................................10-1
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LIST OF TABLES
Table Number 3-1 3-2 3-3 3-4 3-5 3-6 3-7 3-8 4-1 5-1 5-2 6-1 6-2 6-3 7-1 7-2 8-1 8-2 9-1 9-2 9-3 9-4 9-5 TITLE Page Number
MUL instruction.......................................................................................................3-5 Register/memory instructions.................................................................................3-5 Branch instructions .................................................................................................3-6 Bit manipulation instructions...................................................................................3-6 Read/modify/write instructions ...............................................................................3-7 Control instructions.................................................................................................3-7 Instruction set .........................................................................................................3-8 M68HC05 opcode map...........................................................................................3-10 Interrupt Priorities ...................................................................................................4-4 Vector Addresses for Interrupts and Reset.............................................................5-3 Register outline.......................................................................................................5-5 Port D Alternate Functions .....................................................................................6-5 Port D Mode Table ..................................................................................................6-5 Port E/SI Mode Selection .......................................................................................6-6 Sub-system Clock Frequency Selection .................................................................7-2 Real Time Interrupt Rates (bus frequency = 4MHz) ...............................................7-6 PS0, PS1: Serial Port Function Selection Bits........................................................8-1 BD0, BD1: Serial Port Transfer Rate Selection .......................................................8-2 Maximum ratings ....................................................................................................9-1 Thermal Characteristics .........................................................................................9-2 DC Electrical Characteristics (5V) ..........................................................................9-3 AC Electrical Characteristics (5V) ..........................................................................9-4 Expanded Bus Timing.............................................................................................9-5
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1
1
INTRODUCTION
1.1 General
The MC68HC05E0 is a high-performance fully-expandable ROM-less member of the M68HC05 Family of microcomputers. The M68HC05 CPU core has been enhanced with two powerful, independently controlled timer subsystems, and a serial interface (SI) which can operate in either SPI (Serial Peripheral Interface) or I2C-bus compatible mode. An external 16-bit address/8-bit data expansion bus and chip-select logic are provided to allow access to external ROM, RAM and I/O. The MC68HC05E0, with 480 bytes of on-chip RAM and 36 I/O port lines, is available in a 68-pin PLCC package.
1.2
* * * * * * * * * * * *
Features
Industry-standard M68HC05 core and instruction set 64 kbyte address range 16-bit address/8-bit data expansion bus to interface to external memory and peripherals Address decoder provides select logic for internal and external areas of the memory map 480 bytes of on-chip RAM. 4 MHz bus frequency Programmable system timing control 36 I/O lines (four 8-bit bidirectional ports, one 4-bit bidirectional port) LED drive capability on 8 I/O pins (Port A) 6-bit timer with 8-bit prescaler 14-bit timer with 8-bit scaler Programmable Real Time Interrupt
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* * * SPI/I2C-bus interface Control signals (for emulation purposes) Temperature range: 0 - 70 oC
OSC1
OSC2
TS
Timer Subsystem Timer A Timer B System Clock Real Time Interrupt Timer
RESET PD0 (P02) PD1 (R/W) PD2 (CS2) PD3 (CS3) PD4 (LIR) PD5 (A13) PD6 (A14) PD7 (A15) INTX Port D Reg Data Dir Reg Accumulator CPU Control Data Dir Reg Port C Reg PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7 PB0 PB1 PB2 Data Dir Reg ALU Port B Reg PB3 PB4 PB5 PB6 PB7 PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7
Index Register Condition Code Register CPU Stack Pointer Program Counter High Serial Peripheral Interface (SPI/I 2C) Program Counter Low
Address Bus A0 - A12 CSROM
Address Decoder
Data Bus D0 - D7
PE0 PE1 PE2 PE3
Port E Reg
Data Dir Reg Static RAM 480 x 8
Data Dir Reg
Port A Reg
TEST VDD (2) VSS (2)
Figure 1-1 Functional Block Diagram
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2
2
FUNCTIONAL PIN DESCRIPTION
All signal inputs on the MC68HC05E0 except RESET and OSC1 are TTL compatible.
2.1
VDD and VSS
Power is supplied to the microcontroller via two VDD and two VSS pins. VDD is the positive supply and VSS is ground.
2.2
OSC1/OSC2
These pins provide control input for an on-chip clock oscillator circuit. A crystal, ceramic resonator or external clock signal connected to these pins provides the oscillator clock. The oscillator frequency is divided by 2 to provide the internal bus frequency.
2.2.1
Crystal
The circuit shown in Figure 2-1(b) is recommended when using a crystal. The internal oscillator is designed to interface with an AT-cut parallel-resonant quartz crystal resonator in the frequency range specified for fosc (refer to Section 9.5). Use of an external CMOS oscillator is recommended when crystals outside the specified ranges are to be used. The crystal and components should be mounted as close as possible to the input pins to minimise output distortion and startup stabilization time.
2.2.2
Ceramic Resonator
A ceramic resonator may be used in place of the crystal in cost-sensitive applications. The circuit in Figure 2-1(b) is recommended when using a ceramic resonator. Figure 2-1(a) lists the
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2
recommended capacitance and feedback resistance values. The manufacturer of the particular ceramic resonator being considered should be consulted for specific information.
2.2.3
External Clock
An external clock should be applied to the OSC1 input with the OSC2 pin not connected, as shown in Figure 2-1(d). The tOXOV or tILCH specifications do not apply when using an external clock input. The equivalent specification of the external clock source should be used in lieu of tOXOV or tILCH.
2.3
RESET
This active low input-only pin is used to reset the MCU. Applying a logic zero to this pin forces the device to a known start-up state. An external RC-circuit can be connected to this pin to generate a power-on reset (POR). In this case, the time constant must be chosen high enough (minimum 100 ms) to allow the oscillator circuit to stabilise. This input has an internal pull-up resistor and an internal Schmitt trigger to improve noise immunity.
2.4
Port A (PA0 - PA7)
Port A is comprised of eight bidirectional pins (PA0 to PA7). The direction and state of each pin is software programmable, and each pin can drive one LED load. All pins are configured as inputs during power-on or reset.
2.5
Port B (PB0 - PB7)
Port B is comprised of eight bidirectional pins (PB0 to PB7). The direction and state of each pin is software programmable. All pins are configured as inputs during power-on or reset.
2.6
Port C (PC0 - PC7)
Port C is comprised of eight bidirectional pins (PC0 to PC7). The direction and state of each pin is software programmable. In addition, each input can be configured to support a wake-up function and trigger a processor interrupt. All pins are configured as inputs during power-on or reset.
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Crystal 2 MHz RSMAX C0 C1 COSC1 COSC2 RP Q 400 5 0.008 15 - 40 15 - 30 10 30 4 MHz 75 7 0.012 15 - 30 15 - 25 10 40 Units pF F pF pF M K R S (typical) C0 C1 C OSC1 C OSC2 RP Q
Ceramic Resonator 2 - 4 MHz 10 40 4.3 30 30 1 - 10 1250 Units pF pF pF pF M -
2
(a) Crystal/Ceramic Resonator Parameters
L
OSC1
C1
Rs
OSC2
C0
MC68HC05E0 OSC1 OSC2
RP
(c) Equivalent Crystal Circuit
COSC1
COSC2
MC68HC05E0 OSC1 OSC2
(b) Crystal/Ceramic Resonator Oscillator Connections
Unconnected External Clock (d) External Clock Source Connections
Figure 2-1 Oscillator Connections
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2.7
Port D (PD0 - PD7)
Port D is comprised of eight bidirectional pins (PD0 to PD7). The direction and state of each pin is software programmable. Alternatively, Port D can be configured to provide address and control lines for interfacing to external memory. During power-on or reset all port pins except PD0 are defined as port inputs: PD0 is defined as an output and generates the internal bus timing signal P02.
2.8
Port E (PE0 - PE3)
Port E is comprised of four bidirectional pins (PE0 to PE3). The direction and state of each pin is software programmable. In addition, Port E can be configured to support the SPI and I2C-bus functions. All pins are configured as inputs during power-on or reset.
2.9
CSROM
This active low output signal is used as a chip select for external ROM. If the XROM bit in the Timer Control Register ($000C) is set to 1, this pin outputs a logic zero when an address in the range $3000 to $FFFF is present on the address bus. CSROM is normally gated with P02 and is only active during the "high" phase of P02. However, writing a logic zero to the XROM bit in the Timer Control Register ($000C) forces CSROM to remain permanently low throughout the full memory map ($0000-$FFFF). Clearing the XROM bit also has the effect of making all data bus lines input only. This feature is intended for use in a two chip system (MC68HC05E0 and ROM/EPROM) and helps minimise the amount of RFI generated by rapid switching of the bus and CSROM lines.
Note:
Although CSROM is permanently low throughout the full memory map, data on the data bus will be ignored between addresses $0000-$01FF. This space is reserved for internal memory in the MC68HC05E0. (The XROM bit does not affect the internal memory map and Read and Write instructions can be executed as normal in this area.)
XROM 1 0
CSROM Pin gated P02 ($3000-$FFFF) always 0 ($0000-$FFFF)
Data Bus Input/Output Input only
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2.10
INTX
INTX is an input pin for external interrupt sources. The interrupt type (edge or level sensitive), value (high of low), as well as interrupt masking can be selected via the Interrupt Control Register.
2
2.11
TS
The active low TS input pin allows the internal timer functions Timer A and Timer B to be halted. This feature is particularly useful in the emulation environment.
2.12
TEST
The TEST input is only required for factory testing of internal functions. It must not be used during normal operation and must always be connected to VSS.
2.13
Expanded Address Bus (A0 - A12)
Address lines A0 to A12 are always available at these output-only pins and are directly controlled by the processor core. They are intended for accessing external memory. Additional external memory can be addressed by using these lines in conjunction with optional address lines A13 - A15, available on Port D.
2.14
External Data Bus (D0 - D7)
Data signals D0 to D7 are bidirectional signals and permit direct access to the internal data bus. The data bus lines can be configured as input only lines by clearing the XROM bit in the Timer Control Register ($000C); this feature is included to help minimise RFI.
Note:
The address bus lines (A0 - A12) and the data bus lines (D0 - D7) have been designed to have a maximum driving current of 2mA, in order to minimise HF disturbance. The input and output signal levels are CMOS and TTL compatible.
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CPU CORE AND INSTRUCTION SET
This section provides a description of the CPU core registers, the instruction set and the addressing modes of the MC68HC05E0.
3
3.1
Registers
The MCU contains five registers, as shown in the programming model of Figure 3-1. The interrupt stacking order is shown in Figure 3-2.
7 7 15 7 0 Accumulator 0 Index register 0 Program counter Stack pointer Condition code register Carry / borrow Zero Negative Interrupt mask Half carry 0 15 7 0 0000000011 7 0 111HINZC
Figure 3-1 Programming model
3.1.1
Accumulator (A)
The accumulator is a general purpose 8-bit register used to hold operands and results of arithmetic calculations or data manipulations.
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7 Increasing memory address Condition code register Accumulator Index register Program counter high Program counter low Return
0
Stack Interrupt Decreasing memory address
3
3.1.2
Unstack
Figure 3-2 Stacking order
Index register (X)
The index register is an 8-bit register, which can contain the indexed addressing value used to create an effective address. The index register may also be used as a temporary storage area.
3.1.3
Program counter (PC)
The program counter is a 16-bit register, which contains the address of the next byte to be fetched. Although the M68HC05 CPU core can address 64K bytes of memory, the actual address range of the MC68HC05E0 is limited to 4K bytes. The four most significant bits of the program counter are therefore not used and are permanently set to zero.
3.1.4
Stack pointer (SP)
The stack pointer is a 16-bit register, which contains the address of the next free location on the stack. During an MCU reset or the reset stack pointer (RSP) instruction, the stack pointer is set to location $00FF. The stack pointer is then decremented as data is pushed onto the stack and incremented as data is pulled from the stack. When accessing memory, the ten most significant bits are permanently set to 0000000011. These ten bits are appended to the six least significant register bits to produce an address within the range of $00C0 to $00FF. Subroutines and interrupts may use up to 64 (decimal) locations. If 64 locations are exceeded, the stack pointer wraps around and overwrites the previously stored information. A subroutine call occupies two locations on the stack; an interrupt uses five locations.
3.1.5
Condition code register (CCR)
The CCR is a 5-bit register in which four bits are used to indicate the results of the instruction just executed, and the fifth bit indicates whether interrupts are masked. These bits can be individually tested by a program, and specific actions can be taken as a result of their state. Each bit is explained in the following paragraphs.
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Half carry (H) This bit is set during ADD and ADC operations to indicate that a carry occurred between bits 3 and 4. Interrupt (I) When this bit is set, all maskable interrupts are masked. If an interrupt occurs while this bit is set, the interrupt is latched and remains pending until the interrupt bit is cleared. Negative (N) When set, this bit indicates that the result of the last arithmetic, logical, or data manipulation was negative. Zero (Z) When set, this bit indicates that the result of the last arithmetic, logical, or data manipulation was zero. Carry/borrow (C) When set, this bit indicates that a carry or borrow out of the arithmetic logical unit (ALU) occurred during the last arithmetic operation. This bit is also affected during bit test and branch instructions and during shifts and rotates.
3
3.2
Instruction set
The MCU has a set of 62 basic instructions. They can be grouped into five different types as follows: - - - - - Register/memory Read/modify/write Branch Bit manipulation Control
The following paragraphs briefly explain each type. All the instructions within a given type are presented in individual tables. This MCU uses all the instructions available in the M146805 CMOS family plus one more: the unsigned multiply (MUL) instruction. This instruction allows unsigned multiplication of the contents of the accumulator (A) and the index register (X). The high-order product is then stored in the index register and the low-order product is stored in the accumulator. A detailed definition of the MUL instruction is shown in Table 3-1.
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3.2.1
Register/memory Instructions
3
Most of these instructions use two operands. The first operand is either the accumulator or the index register. The second operand is obtained from memory using one of the addressing modes. The jump unconditional (JMP) and jump to subroutine (JSR) instructions have no register operand. Refer to Table 3-2 for a complete list of register/memory instructions.
3.2.2
Branch instructions
These instructions cause the program to branch if a particular condition is met; otherwise, no operation is performed. Branch instructions are two-byte instructions. Refer to Table 3-3.
3.2.3
Bit manipulation instructions
The MCU can set or clear any writable bit that resides in the first 256 bytes of the memory space (page 0). All port data and data direction registers, timer and serial interface registers, control/status registers and a portion of the on-chip RAM reside in page 0. An additional feature allows the software to test and branch on the state of any bit within these locations. The bit set, bit clear, bit test and branch functions are all implemented with single instructions. For the test and branch instructions, the value of the bit tested is also placed in the carry bit of the condition code register. Refer to Table 3-4.
3.2.4
Read/modify/write instructions
These instructions read a memory location or a register, modify or test its contents, and write the modified value back to memory or to the register. The test for negative or zero (TST) instruction is an exception to this sequence of reading, modifying and writing, since it does not modify the value. Refer to Table 3-5 for a complete list of read/modify/write instructions.
3.2.5
Control instructions
These instructions are register reference instructions and are used to control processor operation during program execution. Refer to Table 3-6 for a complete list of control instructions.
3.2.6
Tables
Tables for all the instruction types listed above follow. In addition there is a complete alphabetical listing of all the instructions (see Table 3-7), and an opcode map for the instruction set of the M68HC05 MCU family (see Table 3-8).
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Table 3-1 MUL instruction
X:A X*A Multiplies the eight bits in the index register by the eight Description bits in the accumulator and places the 16-bit result in the concatenated accumulator and index register. H : Cleared I : Not affected Condition N : Not affected codes Z : Not affected C : Cleared Source MUL Addressing mode Cycles Bytes Opcode Form Inherent 11 1 $42 Operation
3
Table 3-2 Register/memory instructions
Addressing modes Immediate Mnemonic Direct Extended Indexed (no offset) # Cycles Opcode Opcode # Bytes Indexed (8-bit offset) # Cycles Opcode # Bytes Indexed (16-bit offset) # Cycles 5 5 6 6 5 5 5 5 5 5 5 5 5 5 4 7 # Bytes 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
# Cycles
# Cycles
Function Load A from memory Load X from memory Store A in memory Store X in memory Add memory to A Add memory and carry to A Subtract memory Subtract memory from A with borrow AND memory with A OR memory with A Exclusive OR memory with A Arithmetic compare A with memory Arithmetic compare X with memory Bit test memory with A (logical compare) Jump unconditional Jump to subroutine
LDA LDX STA STX ADD ADC SUB SBC AND ORA EOR CMP CPX BIT JMP JSR
A6 AE
2 2
2 2
B6 BE B7 BF
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
3 3 4 4 3 3 3 3 3 3 3 3 3 3 2 5
C6 CE C7 CF CB C9 C0 C2 C4 CA C8 C1 C3 C5 CC CD
3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
# Cycles 4 4 5 5 4 4 4 4 4 4 4 4 4 4 3 6
Opcode
Opcode
Opcode
# Bytes
# Bytes
# Bytes
F6 FE F7 FF FB F9 F0 F2 F4 FA F8 F1 F3 F5 FC FD
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
3 3 4 4 3 3 3 3 3 3 3 3 3 3 2 5
E6 EE E7 EF EB E9 E0 E2 E4 EA E8 E1 E3 E5 EC ED
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
4 4 5 5 4 4 4 4 4 4 4 4 4 4 3 6
D6 DE D7 DF DB D9 D0 D2 D4 DA D8 D1 D3 D5 DC DD
AB A9 A0 A2 A4 AA A8 A1 A3 A5
2 2 2 2 2 2 2 2 2 2
2 2 2 2 2 2 2 2 2 2
BB B9 B0 B2 B4 BA B8 B1 B3 B5 BC BD
MC68HC05E0
CPU CORE AND INSTRUCTION SET
MOTOROLA 3-5
Table 3-3 Branch instructions
Relative addressing mode Opcode # Bytes # Cycles 20 2 3 21 2 3 22 2 3 23 2 3 24 2 3 24 2 3 25 2 3 25 2 3 26 2 3 27 2 3 28 2 3 29 2 3 2A 2 3 2B 2 3 2C 2 3 2D 2 3 2E 2 3 2F 2 3 AD 2 6
3
Function Branch always Branch never Branch if higher Branch if lower or same Branch if carry clear (Branch if higher or same) Branch if carry set (Branch if lower) Branch if not equal Branch if equal Branch if half carry clear Branch if half carry set Branch if plus Branch if minus Branch if interrupt mask bit is clear Branch if interrupt mask bit is set Branch if interrupt line is low Branch if interrupt line is high Branch to subroutine
Mnemonic BRA BRN BHI BLS BCC (BHS) BCS (BLO) BNE BEQ BHCC BHCS BPL BMI BMC BMS BIL BIH BSR
Table 3-4 Bit manipulation instructions
Addressing modes Bit set/clear Bit test and branch Opcode # Bytes # Cycles Opcode # Bytes # Cycles 2*n 3 5 01+2*n 3 5 10+2*n 2 5 11+2*n 2 5
Function Branch if bit n is set Branch if bit n is clear Set bit n Clear bit n
Mnemonic BRSET n (n=0-7) BRCLR n (n=0-7) BSET n (n=0-7) BCLR n (n=0-7)
MOTOROLA 3-6
CPU CORE AND INSTRUCTION SET
MC68HC05E0
Table 3-5 Read/modify/write instructions
Addressing modes Inherent (A) Mnemonic # Cycles Opcode Inherent (X) # Cycles Opcode Opcode Direct Indexed (no offset) # Cycles # Cycles Opcode # Bytes Indexed (8-bit offset) # Cycles Opcode # Bytes
3
6 6 6 6 6 6 6 6 6 6 5
# Bytes
# Bytes
Function Increment Decrement Clear Complement Negate (two's complement) Rotate left through carry Rotate right through carry Logical shift left Logical shift right Arithmetic shift right Test for negative or zero Multiply
INC DEC CLR COM NEG ROL ROR LSL LSR ASR TST MUL
4C 4A 4F 43 40 49 46 48 44 47 4D 42
1 1 1 1 1 1 1 1 1 1 1 1
3 5C 3 5A 3 5F 3 53 3 50 3 59 3 56 3 58 3 54 3 57 3 5D 11
1 1 1 1 1 1 1 1 1 1 1
3 3 3 3 3 3 3 3 3 3 3
3C 3A 3F 33 30 39 36 38 34 37 3D
# Bytes 2 2 2 2 2 2 2 2 2 2 2
5 5 5 5 5 5 5 5 5 5 4
7C 7A 7F 73 70 79 76 78 74 77 7D
1 1 1 1 1 1 1 1 1 1 1
5 5 5 5 5 5 5 5 5 5 4
6C 6A 6F 63 60 69 66 68 64 67 6D
2 2 2 2 2 2 2 2 2 2 2
Table 3-6 Control instructions
Inherent addressing mode Opcode # Bytes # Cycles 97 1 2 9F 1 2 99 1 2 98 1 2 9B 1 2 9A 1 2 83 1 10 81 1 6 80 1 9 9C 1 2 9D 1 2 8E 1 2 8F 1 2
Function Transfer A to X Transfer X to A Set carry bit Clear carry bit Set interrupt mask bit Clear interrupt mask bit Software interrupt Return from subroutine Return from interrupt Reset stack pointer No-operation Stop Wait
Mnemonic TAX TXA SEC CLC SEI CLI SWI RTS RTI RSP NOP STOP WAIT
MC68HC05E0
CPU CORE AND INSTRUCTION SET
MOTOROLA 3-7
Table 3-7 Instruction set
Addressing modes EXT REL IX IX1 Condition codes I NZC * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * 0 * * * * * * * * * * * * * * * * * * * * * * * * * * * 0 * * * * * * * * * * * * * * * * * * * * * * * * * 1 * * * * * * * * * * * * * * * * * * * * * * * 0 * *
Mnemonic
3
INH
IMM
DIR
IX2
BSC BTB
ADC ADD AND ASL ASR BCC BCLR BCS BEQ BHCC BHCS BHI BHS BIH BIL BIT BLO BLS BMC BMI BMS BNE BPL BRA BRN BRCLR BRSET BSET BSR CLC CLI CLR CMP
H * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Condition code symbols Address mode abbreviations
BSC Bit set/clear BTB DIR EXT INH Bit test & branch Direct Extended Inherent IMM IX IX1 IX2 REL Immediate Indexed (no offset) Indexed, 1 byte offset Indexed, 2 byte offset Relative H I N Z C Half carry (from bit 3) Interrupt mask Negate (sign bit) Zero Carry/borrow * ? 0 1 Tested and set if true, cleared otherwise Not affected Load CCR from stack Cleared Set
Not implemented
MOTOROLA 3-8
CPU CORE AND INSTRUCTION SET
MC68HC05E0
Table 3-7 Instruction set (Continued)
Addressing modes EXT REL IX IX1 Condition codes I NZC * * * * * * * * * * * * * * * * * * ? * * * 1 * 0 * * 1 * * * 0 * * 0 * * * ? * * * * * * * * * * * * * ? * * * * * * * * 1 * * * * * * * 0 * * * ? * 1 * * * * * * * * *
Mnemonic COM CPX DEC EOR INC JMP JSR LDA LDX LSL LSR MUL NEG NOP ORA ROL ROR RSP RTI RTS SBC SEC SEI STA STOP STX SUB SWI TAX TST TXA WAIT
INH
IMM
DIR
IX2
BSC BTB
H * * * * * * * * * * * 0 * * * * * * ? * * * * * * * * * * * * *
3
Condition code symbols Address mode abbreviations
BSC Bit set/clear BTB DIR EXT INH Bit test & branch Direct Extended Inherent IMM IX IX1 IX2 REL Immediate Indexed (no offset) Indexed, 1 byte offset Indexed, 2 byte offset Relative H I N Z C Half carry (from bit 3) Interrupt mask Negate (sign bit) Zero Carry/borrow * ? 0 1 Tested and set if true, cleared otherwise Not affected Load CCR from stack Cleared Set
Not implemented
MC68HC05E0
CPU CORE AND INSTRUCTION SET
MOTOROLA 3-9
3
Control
High
MOTOROLA 3-10
DIR 3 0011 Low
3 IX 3 3
High NEG
DIR 1 INH 1 INH 2 IX1 1 IX 1 5
Low
Bit manipulation BTB BSC 0 1 0000 0001 INH 4 0100 NEGA RTS
1 INH 2 INH 6 2 3
Branch REL 2 0010 IX 7 0111
6
Read/modify/write INH IX1 5 6 0101 0110 INH 8 1000
5
INH 9 1001
9
IMM A 1010 SUB CMP SBC
2 IMM 2 2 IMM 2 2 2
DIR B 1011 SUB CMP SBC CPX AND BIT LDA STA
2 DIR 3 4 DIR 3 3 DIR 3 3 DIR 3 3 DIR 3 3 DIR 3 3 DIR 3 3 3
Register/memory EXT IX2 C D 1100 1101 IX1 E 1110
5
IX F 1111
4
BRSET0
REL 2 3
5
BSET0 CMP SBC CPX AND BIT LDA STA EOR ADC ORA ADD JMP
2 DIR 3 3 EXT 3 5 EXT 3 4 EXT 3 4 EXT 3 4 EXT 3 4 EXT 3 4 EXT 3 4
5
BRA CMP SBC CPX AND BIT LDA STA EOR
EXT 3 4 EXT 3 4 EXT 3 4 IX2 2 5 IX2 2 5 IX2 2 5 IX2 2 5 IX2 2 5
NEGX CMP SBC CPX AND BIT
IX2 2 5 IX1 1 4 IX1 1 4 IX1 1 4 IX1 1 4 IX1 1 4
3
NEG CMP SBC CPX AND BIT LDA
IX2 2 6 IX1 1 4
NEG
RTI
SUB
4
SUB
SUB
SUB
3
BRCLR0
REL 3
BTB 2 5
BCLR0 MUL
1 11 REL 3
BSC 2 5 IX 3
BRN
3
BRSET1 COM LSR
DIR 1 INH 1 INH 2 IX1 1 IX 2 DIR 1 5 5
BTB 2 5 INH 3
BSET1 COMA LSRA BIT
2 IMM 2 2 INH 1 3
BSC 2 5
BHI COMX LSRX
INH 2 3 3
3
BRCLR1
REL 2 3
BTB 2 5
BCLR1 LSR
IX1 1 6
BSC 2 5
BLS LSR
IX 1 5 INH 2
COM AND
IMM 2 2
6
COM
5
SWI
10
CPX
IMM 2 2
IX 3 IX 3 IX 3
3
BRSET2
REL 2 3 REL 3
BTB 2 5
BSET2
BSC 2 5
BCC
3
BRCLR2 ROR ASR LSL ROL DEC
DIR 1 INH 1 INH 2 IX1 1 IX 1 DIR 1 5 DIR 1 5 DIR 1 5 DIR 1 5 5
BTB 2 5
BCLR2 RORA ASRA LSLA ROLA DECA SEI
1 INH 2 2 INH 1 3 INH 1 3 INH 1 3 INH 1 3 3
BSC 2 5
BCS RORX ASRX LSLX ROLX DECX ADD
IMM 2 2 IMM 2 INH 2 3 INH 2 3 INH 2 3 INH 2 3 3
3
BRSET3
REL 2 3
BTB 2 5
BSET3 ASR LSL ROL DEC
IX1 1 6 IX1 1 6 IX1 1 6 IX1 1 6
BSC 2 5
BNE ASR LSL ROL DEC
IX 5 1 IX 5 1 IX 5 1 IX 5 2 IMM 2
ROR TAX CLC SEC CLI
INH 2 2 INH 2 2 INH 2 2
6
ROR
5
LDA
IMM 2 2
LDA STA
IX2 2 5 IX2 2 5 IX1 1 5
IX 3 IX 4
3
BRCLR3
REL 2 3
BTB 2 5
BCLR3 EOR ADC ORA
IMM 2 2 IMM 2 2 2
BSC 2 5 DIR 3 3 DIR 3 3 DIR 3 3 EXT 3 4
BEQ EOR ADC ORA
REL 2 3
STA EOR ADC ORA ADC
IX2 2 5 IX2 2 5 IX1 1 4 IX1 1 4 IX1 1 4
3
BRSET4
REL 2 3 REL 2 3 REL 3
BTB 2 5
BSET4
BSC 2 5
BHCC
EOR ADC ORA ADD ADD ADD ORA
IX1 1 4
IX 3 IX 3 IX 3 IX 3
3
BRCLR4
BTB 2 5
BCLR4
BSC 2 5
BHCS
3
BRSET5
BTB 2 5
BSET5
BSC 2 5
BPL
3
BRCLR5 INC TST
DIR 1 INH 1 INH 2 IX1 1 IX 1 DIR 1 4 5
BTB 2 5
BCLR5 INCA TSTA STOP
1 2 2 INH 1 3 3
BSC 2 5
BMI INCX TSTX
INH 2 3 3
ADD
DIR 3 2
3
BRSET6
REL 2 3
BTB 2 5
BSET6 TST
IX1 1 5
BSC 2 5
BMC TST
IX 4 1
INC NOP
INH 2 INH 2
6
INC
5
RSP
INH 2 2
JMP BSR LDX
6 REL 2 2 IMM 2
EXT 3 3 DIR 3 5 EXT 3 6
JMP JSR LDX JSR
DIR 3 3
IX2 2 4 IX2 2 7
JMP JSR LDX
EXT 3 4
IX1 1 3 IX1 1 6
JMP JSR LDX
IX2 2 5
IX 2 IX 5
3
BRCLR6
REL 2 3 REL 3
BTB 2 5
BCLR6
BSC 2 5
BMS
JSR LDX
IX1 1 4
3
Table 3-8 M68HC05 opcode map
BRSET7 CLR
DIR 1 INH 1 INH 2 IX1 1 IX 1 5
BTB 2 5
BSET7 CLRA
3
BSC 2 5
BIL CLRX
3
LDX TXA
2 INH 2
IX 3
3
CPU CORE AND INSTRUCTION SET
CLR
6
0 0000 1 0001 2 0010 3 0011 4 0100 5 0101 6 0110 7 0111 8 1000 9 1001 A 1010 B 1011 C 1100 D 1101 E 1110 F 1111 CLR
5
BRCLR7
REL 2
BTB 2 5
BCLR7
BSC 2 5
BIH
WAIT
INH 2 INH 1
STX
DIR 3 4 DIR 3
STX
EXT 3 5 EXT 3
STX
IX2 2 6 IX2 2
STX
IX1 1 5 IX1 1
STX
IX 4 IX
3
BTB 2
BSC 2
0 0000 1 0001 2 0010 3 0011 4 0100 5 0101 6 0110 7 0111 8 1000 9 1001 A 1010 B 1011 C 1100 D 1101 E 1110 F 1111
Abbreviations for address modes and registers
Legend F 1111 Mnemonic
1
Opcode in hexadecimal Opcode in binary SUB Not implemented Bytes Cycles Address mode
3 IX
BSC BTB DIR EXT INH IMM IX IX1 IX2 REL A X Indexed (no offset) Indexed, 1 byte (8-bit) offset Indexed, 2 byte (16-bit) offset Relative Accumulator Index register
Bit set/clear Bit test and branch Direct Extended Inherent Immediate
0 0000
MC68HC05E0
3.3
Addressing modes
Ten different addressing modes provide programmers with the flexibility to optimize their code for all situations. The various indexed addressing modes make it possible to locate data tables, code conversion tables and scaling tables anywhere in the memory space. Short indexed accesses are single byte instructions; the longest instructions (three bytes) enable access to tables throughout memory. Short absolute (direct) and long absolute (extended) addressing are also included. One or two byte direct addressing instructions access all data bytes in most applications. Extended addressing permits jump instructions to reach all memory locations. The term `effective address' (EA) is used in describing the various addressing modes. The effective address is defined as the address from which the argument for an instruction is fetched or stored. The ten addressing modes of the processor are described below. Parentheses are used to indicate `contents of' the location or register referred to. For example, (PC) indicates the contents of the location pointed to by the PC (program counter). An arrow indicates `is replaced by' and a colon indicates concatenation of two bytes. For additional details and graphical illustrations, refer to the M6805 HMOS/M146805 CMOS Family Microcomputer/ Microprocessor User's Manual or to the M68HC05 Applications Guide.
3
3.3.1
Inherent
In the inherent addressing mode, all the information necessary to execute the instruction is contained in the opcode. Operations specifying only the index register or accumulator, as well as the control instruction, with no other arguments are included in this mode. These instructions are one byte long.
3.3.2
Immediate
In the immediate addressing mode, the operand is contained in the byte immediately following the opcode. The immediate addressing mode is used to access constants that do not change during program execution (e.g. a constant used to initialize a loop counter). EA = PC+1; PC PC+2
3.3.3
Direct
In the direct addressing mode, the effective address of the argument is contained in a single byte following the opcode byte. Direct addressing allows the user to directly address the lowest 256 bytes in memory with a single two-byte instruction. EA = (PC+1); PC PC+2 Address bus high 0; Address bus low (PC+1)
MC68HC05E0
CPU CORE AND INSTRUCTION SET
MOTOROLA 3-11
3.3.4
Extended
3
In the extended addressing mode, the effective address of the argument is contained in the two bytes following the opcode byte. Instructions with extended addressing mode are capable of referencing arguments anywhere in memory with a single three-byte instruction. When using the Motorola assembler, the user need not specify whether an instruction uses direct or extended addressing. The assembler automatically selects the short form of the instruction. EA = (PC+1):(PC+2); PC PC+3 Address bus high (PC+1); Address bus low (PC+2)
3.3.5
Indexed, no offset
In the indexed, no offset addressing mode, the effective address of the argument is contained in the 8-bit index register. This addressing mode can access the first 256 memory locations. These instructions are only one byte long. This mode is often used to move a pointer through a table or to hold the address of a frequently referenced RAM or I/O location. EA = X; PC PC+1 Address bus high 0; Address bus low X
3.3.6
Indexed, 8-bit offset
In the indexed, 8-bit offset addressing mode, the effective address is the sum of the contents of the unsigned 8-bit index register and the unsigned byte following the opcode. Therefore the operand can be located anywhere within the lowest 511 memory locations. This addressing mode is useful for selecting the mth element in an n element table. EA = X+(PC+1); PC PC+2 Address bus high K; Address bus low X+(PC+1) where K = the carry from the addition of X and (PC+1)
3.3.7
Indexed, 16-bit offset
In the indexed, 16-bit offset addressing mode, the effective address is the sum of the contents of the unsigned 8-bit index register and the two unsigned bytes following the opcode. This address mode can be used in a manner similar to indexed, 8-bit offset except that this three-byte instruction allows tables to be anywhere in memory. As with direct and extended addressing, the Motorola assembler determines the shortest form of indexed addressing. EA = X+[(PC+1):(PC+2)]; PC PC+3 Address bus high (PC+1)+K; Address bus low X+(PC+2) where K = the carry from the addition of X and (PC+2)
MOTOROLA 3-12
CPU CORE AND INSTRUCTION SET
MC68HC05E0
3.3.8
Relative
The relative addressing mode is only used in branch instructions. In relative addressing, the contents of the 8-bit signed byte (the offset) following the opcode are added to the PC if, and only if, the branch conditions are true. Otherwise, control proceeds to the next instruction. The span of relative addressing is from -126 to +129 from the opcode address. The programmer need not calculate the offset when using the Motorola assembler, since it calculates the proper offset and checks to see that it is within the span of the branch. EA = PC+2+(PC+1); PC EA if branch taken; otherwise EA = PC PC+2
3
3.3.9
Bit set/clear
In the bit set/clear addressing mode, the bit to be set or cleared is part of the opcode. The byte following the opcode specifies the address of the byte in which the specified bit is to be set or cleared. Any read/write bit in the first 256 locations of memory, including I/O, can be selectively set or cleared with a single two-byte instruction. EA = (PC+1); PC PC+2 Address bus high 0; Address bus low (PC+1)
3.3.10
Bit test and branch
The bit test and branch addressing mode is a combination of direct addressing and relative addressing. The bit to be tested and its condition (set or clear) is included in the opcode. The address of the byte to be tested is in the single byte immediately following the opcode byte (EA1). The signed relative 8-bit offset in the third byte (EA2) is added to the PC if the specified bit is set or cleared in the specified memory location. This single three-byte instruction allows the program to branch based on the condition of any readable bit in the first 256 locations of memory. The span of branch is from -125 to +130 from the opcode address. The state of the tested bit is also transferred to the carry bit of the condition code register. EA1 = (PC+1); PC PC+2 Address bus high 0; Address bus low (PC+1) EA2 = PC+3+(PC+2); PC EA2 if branch taken; otherwise PC PC+3
MC68HC05E0
CPU CORE AND INSTRUCTION SET
MOTOROLA 3-13
3
THIS PAGE LEFT BLANK INTENTIONALLY
MOTOROLA 3-14
CPU CORE AND INSTRUCTION SET
MC68HC05E0
4
RESETS, INTERRUPTS AND LOW POWER MODES
4.1 Resets
4
The MCU can be reset by the initial power-on reset function or by an active low level applied to the RESET pin (see Figure 4-1).
tVDDR VDD VDD threshold (1-2V typical) tOXOV OSC1 tPORL Internal processor clock tCYC
RESET
(Internal power-on reset)
tRL (or tDOGL)
(External hardware reset)
Internal address bus Internal data bus
7FFE 7FFE 7FFE 7FFE 7FFF
New PC
7FFE 7FFE 7FFE 7FFE
7FFF
New PC
Reset sequence
New PCH New PCL Op code
Reset sequence
New PCH New PCL Op code
Program execution begins
Program execution begins
Figure 4-1 Power-on Reset and RESET
MC68HC05E0
RESETS, INTERRUPTS AND LOW POWER MODES
MOTOROLA 4-1
4.1.1
Power-on Reset
4
A power-on reset occurs when a positive transition is detected on VDD. The power-on reset function is strictly for power turn-on conditions and should not be used to detect drops in the power supply voltage. The power-on circuitry provides for a 4064 tCYC delay from the time that the oscillator becomes active. If the external RESET pin is low at the end of the 4064 cycle time-out, the processor remains in the reset state until RESET goes high. The user must ensure that the voltage on VDD has risen to a point where the MCU can operate properly by the time the 4064 cycles have elapsed. If there is doubt, the external RESET pin should remain low until the voltage on VDD has reached the specified minimum operating voltage.
4.1.2
RESET Pin
When the oscillator is running in a stable state, the MCU is reset when a logic zero is applied to the RESET input for a minimum period of one and one-half machine cycles (tCYC). This pin contains an internal Schmitt Trigger as part of its input to improve noise immunity.
4.2
Interrupts
The MCU can be interrupted by seven different sources: six maskable hardware interrupts and one non-maskable software interrupt: * * * * * * * External signal on the INTX pin, Real Time Interrupt, Port C Wake-up, Timer A, Timer B, Serial Interface, Software Interrupt instruction (SWI).
Interrupts cause the processor to save the register contents on the stack and to set the interrupt mask (I bit) to prevent additional interrupts. The RTI instruction (ReTurn from Interrupt) causes the register contents to be recovered from the stack and normal processing to resume. Unlike reset, hardware interrupts do not cause the current instruction execution to be halted, but are considered pending until the current instruction is complete.
Note:
The current instruction is the one already fetched and being operated on.
MOTOROLA 4-2
RESETS, INTERRUPTS AND LOW POWER MODES
MC68HC05E0
When the current instruction is complete, the processor checks all pending hardware interrupts. If interrupts are not masked (CCR I bit clear), the processor proceeds with interrupt processing; otherwise, the next instruction is fetched and executed. Internal circuitry generates a processor interrupt signal IRQB if an interrupt occurs via either the external interrupt pin INTX, the wake-up function on Port C, or a real time interrupt (see Figure 4-2). The interrupting source can be determined by testing the state of the INTFX, WAKF and RTIF flag bits.
4
Wake-up (Port C)
WAKF RTIE
Real Time Interrupt
IRQB
RTIF
INTFX
INTMX
INTXP
Pad
INTX
Figure 4-2 Internal Processor Interrupt Signal IRQB
Note:
Acknowledging an interrupt signal too early could have an effect on the BIH and BIL command functions.
MC68HC05E0
RESETS, INTERRUPTS AND LOW POWER MODES
MOTOROLA 4-3
Table 4-1 shows the relative priority of all the possible interrupt sources. Internally, the External Interrupt, Real Time Interrupt, and Wake-up signals are "ORed" to generate the CPU interrupt signal IRQB. The source responsible for generating the IRQB interrupt can be determined by examining the interrupt flag bits associated with these sources.
Note:
4
The external interrupt INTX can be disabled by setting the External Interrupt Mask bit (INTMX) in the Interrupt Control Register ($000E).
Table 4-1 Interrupt Priorities Source Real time interrupt External interrupt (INTX) Wake-up (Port C) Timer A Timer B Serial interface Vector address $FFFA, $FFFB $FFF8, $FFF9 $FFF6, $FFF7 $FFF4, $FFF5 Priority highest
lowest
For example, if both an external interrupt and a Timer A interrupt are pending at the end of an instruction execution, the external interrupt is serviced first. The software interrupt SWI is executed in the same way as any other instruction, regardless of the state of the I-bit.
4.2.1
Hardware Controlled Interrupt Sequence
The following three functions (RESET, STOP, and WAIT) are not in the strictest sense interrupts. However, they are acted upon in a similar manner. Flowcharts for hardware interrupts are shown in Figure 4-3, and for STOP and WAIT in Figure 4-4. RESET: A reset condition causes the program to vector to its starting address which is specified by the contents of memory locations $FFFE (MSB) and $FFFF (LSB). The I bit in the condition code register is also set. The STOP instruction causes the oscillator to be turned off and the processor to "sleep" until an external interrupt (INTX) (if enabled), a wake-up interrupt (if enabled) or reset occurs. The WAIT instruction causes all processor clocks to stop, but leaves the timer clock running. This "rest" state of the processor can be cleared by reset, an external interrupt (INTX) (if enabled), a wake-up interrupt or a Timer/SI interrupt. There are no special wait vectors for these individual interrupts.
STOP:
WAIT:
MOTOROLA 4-4
RESETS, INTERRUPTS AND LOW POWER MODES
MC68HC05E0
From RESET
Yes
Is I-bit set ? No
4
Yes Clear IRQB Request latch
INTX, RTI, or Wake-up ? No
Timer A ? No
Yes
Timer B ? No
Yes
SI ? No
Yes
Stack PC/X/A/CCR
Set I-bit Fetch Instruction Load PC from: IRQB: $1FFA - $1FFB Timer A: $1FF8 - $1FF9 Timer B: $1FF6 - $1FF7 SI: $1FF4 - $1FF5
Execute Instruction
Figure 4-3 Hardware Interrupt Flow Chart
MC68HC05E0
RESETS, INTERRUPTS AND LOW POWER MODES
MOTOROLA 4-5
STOP
WAIT
Stop Oscillator and all clocks Clear I Bit
Oscillator active Processor clock stopped All other clocks active Clear I Bit
4
No RESET ? Yes RESET ? Yes No No INTX or Wake-up ? Yes INTX, RTI or Wake-up ? Yes TIMER A ? Yes TIMER B ? Yes SI ? Yes Turn on oscillator Wait for stabilisation time delay Turn on oscillator Wait for stabilisation time delay Restart Internal Clocks Restart Internal Clocks Restart Internal Clocks Restart Internal Clocks Restart Internal Clocks No No No No
Stack PC/X/A/CC
Reset Processor
Reset Processor
Stack PC/X/A/CC
Stack PC/X/A/CC
Stack PC/X/A/CC
Stack PC/X/A/CC
Set I-bit
Set I-bit
Set I-bit
Set I-bit
Set I-bit
Load PC from $1FFA, $1FFB
Load PC from $1FFE, $1FFF
Load PC from $1FFE, $1FFF
Load PC from $1FFA, $1FFB
Load PC from $1FF8, $1FF9
Load PC from $1FF6, $1FF7
Load PC from $1FF4, $1FF5
Fetch Instruction
Fetch Instruction
Figure 4-4 STOP/WAIT Flow Chart
MOTOROLA 4-6
RESETS, INTERRUPTS AND LOW POWER MODES
MC68HC05E0
4.2.2
Non-Maskable Software interrupt (SWI)
The software interrupt SWI is an executable instruction and a non-maskable interrupt: it is executed regardless of the state of the I bit in the CCR. If the I bit is zero (interrupts enabled), SWI is executed after interrupts which were pending when the SWI was fetched, but before interrupts generated after the SWI was fetched. The SWI interrupt service routine address is specified by the contents of memory locations $FFFC and $FFFD.
4
4.2.3 Maskable Hardware Interrupts
If the interrupt mask bit (I bit) of the CCR is set, all maskable interrupts (internal and external) are disabled. Clearing the I bit enables interrupts.
Note:
The internal interrupt latch is cleared in the first part of the interrupt service routine; therefore, one external interrupt pulse could be latched and serviced as soon as the I bit is cleared.
4.2.3.1
External Interrupt (INTX)
The interrupt request is latched immediately following the selected edge on the INTX pin. It is then synchronized internally and serviced by the routine that has its start address contained in memory locations $FFFA and $FFFB. The External Interrupt Mask bit (INTMX) in the Interrupt Control Register ($000E) allows this interrupt to be masked from the processor.
4.2.3.2
Real Time Interrupt
The interrupt request is latched when the Real Time Interrupt Timer times out. It is then synchronized internally and serviced by the routine that has its start address contained in memory locations $FFFA and $FFFB. The Real Time Interrupt Enable bit (RTIE) in the RTI Control Register ($0018) allows this interrupt to be masked from the processor.
4.2.3.3
Port C Wake-up
The interrupt request is latched when a defined Wake-up signal appears on one of the pins of Port C. It is then synchronized internally and serviced by the routine that has its start address contained in memory locations $FFFA and $FFFB. The Wake-up Enable bits (WEn) in the Wake-up Enable Register ($0013) allow these interrupts to be masked from the processor.
MC68HC05E0
RESETS, INTERRUPTS AND LOW POWER MODES
MOTOROLA 4-7
4.2.3.4
Timer A Interrupt
The interrupt request is latched when Timer A times out. It is then synchronized internally and serviced by the routine that has its address contained in memory locations $FFF8 and $FFF9. The Timer A Interrupt Mask bit (INTMA) in the Interrupt Control Register ($000E) allows this interrupt to be masked from the processor.
4
4.2.3.5
Timer B Interrupt
The interrupt request is latched when Timer B times out. It is then synchronized internally and serviced by the routine that has its start address contained in memory locations $FFF6 and $FFF7. The Timer B Interrupt Mask bit (INTMB) in the Interrupt Control Register ($000E) allows this interrupt to be masked from the processor.
4.2.3.6
SI Interrupt
The interrupt request is latched immediately after each data transfer. It is then synchronized internally and serviced by the routine that has its start address contained in memory locations $FFF4 and $FFF5. The SI Enable bit (SIE) in the Port E/SI Mode Register ($0010) allows this interrupt to be enabled or disabled (see Section 8).
4.2.4
Interrupt Control
The Interrupt Control Register ($000E) allows masking and provides acknowledgement of the interrupt signals:
Address Interrupt control register $000E bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 State on reset
WAKF INTXP INTFB INTFA INTFX INTMB INTMA INTMX 0000 0001
INTMX, INTMA, INTMB These three interrupt mask bits permit INTX (external interrupt), Timer A and Timer B interrupt signals to be masked from the processor: 1 (set) - Interrupts not masked Interrupts masked
0 (clear) -
After a hardware reset, only external interrupts are permitted.
MOTOROLA 4-8
RESETS, INTERRUPTS AND LOW POWER MODES
MC68HC05E0
INTFX, INTFA, INTFB These three bits (Interrupt Flag and Acknowledge) indicate the occurrence of interrupt signals from INTX (external interrupt), Timer A and Timer B. Timers A and B generate interrupt signals when their final values are reached: 1 (set) - Interrupt has occurred Interrupt has not occurred
0 (clear) -
Writing a "0" to one of these bits acknowledges the interrupt and resets the interrupt signal. INTXP The INTXP bit (Program External Interrupt) selects which signal edge or level on the INTX input generates an external interrupt: 1 (set) - Interrupt on rising edge or logic high level Interrupt on falling edge or logic low level
4
0 (clear) -
This bit only influences the effect of a signal coming from an external source (INTX) but not the function of the IRQB signal to the microprocessor. WAKF The WAKF bit (Wake-up Flag) indicates that an interrupt was generated by the Wake-up function on Port C: 1 (set) - Interrupt caused by wake-up function Interrupt not caused by wake-up function
0 (clear) -
Writing a "0" to one of these bits acknowledges the interrupt and resets the interrupt signal. Additional control of external interrupts is achieved via the PITX bit in the Timer Control Register ($000C):
Address Timer control register $000C bit 7 SC1 bit 6 SC0 bit 5 PITX bit 4 PITW bit 3 1 bit 2 XHOM bit 1 CEIB bit 0 CEIA State on reset uuuu 11uu
PITX The PITX bit (Program Interrupt Type eXternal) provides additional control of external interrupts by selecting either edge or level sensitive triggering. 1 (set) - Level-triggered interrupt selected Edge-triggered only interrupt selected
0 (clear) -
MC68HC05E0
RESETS, INTERRUPTS AND LOW POWER MODES
MOTOROLA 4-9
Note:
PITW (Program Interrupt Type Wake-up function), bit 4 of the Timer Control Register ($000C) provides additional control of wake-up interrupts on Port C by selecting either edge or level sensitive triggering.
4.3
Low Power Modes STOP
4
4.3.1
The STOP instruction places the MCU in its lowest power consumption mode. The processor can only be started again by an external interrupt (on the INTX pin) (if enabled), a wake-up interrupt (if enabled) or reset. The oscillator is stopped, all CPU and timer functions are stopped, and an oscillator stabilisation delay of 4064 cycles is required to start the processor again.
Note:
The RTI Timer restarts immediately after exiting the STOP state.
During the STOP mode, the RTI interrupt flag and interrupt enable bits are cleared by internal hardware to remove any pending interrupt requests. The RTI Timer prescaler is also cleared. The I bit in the CCR is cleared to enable external interrupts or wake-up function interrupts. All other bits and registers, and memory remain unaltered. All input/output lines remain unchanged.
Note:
Pending interrupts from Timer A, Timer B, and SI are not cleared by the stop instruction. The external interrupt INTX can be disabled by the External Interrupt Mask bit (INTMX) in the Interrupt Control Register ($000E).
4.3.2
WAIT
The WAIT instruction places the MCU in a low-power consumption mode, but the WAIT mode consumes more power than the STOP mode. All CPU action is suspended, but the timers remain active. An interrupt from the timer can cause the MCU to exit the WAIT mode. During the WAIT mode, the I bit in the CCR is cleared to enable interrupts. All other registers, memory and input/output lines remain in their previous state.
MOTOROLA 4-10
RESETS, INTERRUPTS AND LOW POWER MODES
MC68HC05E0
5
MEMORY AND ADDRESSING
5
5.1 Memory Map
As shown in Figure 5-1, the MC68HC05E0 is capable of addressing a full 65536 bytes of memory and I/O using a non-multiplexed bus. The address space is divided into internal memory space and external memory space as shown in the memory map. The internal memory space is located within the first 512 bytes of memory (pages 0 and 1) and contains the I/O port data and data registers, all the timer, Serial Interface and wake-up control and data registers, and 480 bytes of RAM. Program writes to on-chip locations are repeated on the external bus enabling off-chip memory to duplicate the contents of on-chip memory. Program reads from on-chip locations also appear on the external bus, but the CPU accepts data only from the addressed on-chip locations, and ignores data appearing on the input bus.
5.2
RAM
480 bytes of on-chip static RAM are located from $0020 to $01FF. The processor stack starts at $00FF and is limited to 64 bytes ($00C0 to $00FF). When the stack overflows it wraps round from $00C0 to $00FF, overwriting any existing data.
Note:
Using the stack area for data storage or as temporary work locations requires care to prevent it from being overwritten due to stacking from an interrupt or subroutine call.
External RAM can be located from $0200 to $1FFF and accessed via the external data and address buses. PD2 (Port D, bit 2) can be configured to output a chip select signal (CS2) which can be used to select the external RAM, when an address in this range is present on the address bus.
MC68HC05E0
MEMORY AND ADDRESSING
MOTOROLA 5-1
5.3
ROM
External ROM can be located from $0200 to $FFFF and accessed via the external data and address buses. (Address lines A0 to A12 are always available; PD5 to PD7 (Port D bits 5 to 7) can be configured as address lines A13 to A15 to provide addressing above $8000.) Chip select signal CSROM can be used to select the external ROM, when an address in the range $3000-$FFFF is present on the address bus.
Note:
5
5.4
Writing a logic zero to bit 2 (XROM) of the Timer Control Register ($000C) causes the CSROM output to remain permanently low throughout the full memory map ($0000-$FFFF). Clearing XROM also sets the external data bus lines to INPUT only (See Section 2.9).
Registers
Internal registers associated with the on-board hardware functions are located from $0000 to $001F. All internal registers and their contents are shown in Table 5-1. External I/O (on peripheral devices) can be located from $2000 to $2FFF and accessed via the external data and address buses. PD3 (Port D, bit 3) can be configured to output a chip select signal (CS3) which can be used to select the external I/O, when an address in this range is present on the address bus.
5.5
Vectors
All vectors for reset, hardware interrupts and software interrupt are located at the top of the memory map, from $FFF4 to $FFFF, as shown in Figure 3-1. Each vector location consists of two bytes containing the start address (in ROM) of the reset or interrupt routine (see Table 5-2).
5.6
Address Decoding and System Expansion
The address decoder partitions the entire memory space into RAM, ROM, register and interrupt vector areas. This allows access to external blocks of memory and peripherals as well as to the on-chip RAM and all the registers supporting the on-chip hardware functions. Address bus and data bus lines (A0 to A12 and D0 to D7, respectively) and chip select signal CSROM are always available. In addition, Port D can be configured (via the Port D Mode register) to provide the following address, control and chip select signals:-
MOTOROLA 5-2
MEMORY AND ADDRESSING
MC68HC05E0
Table 5-1 Vector Addresses for Interrupts and Reset
Register N/A CCR Interrupt control RTI control Interrupt control Interrupt control Interrupt control SI S Flag name N/A I-bit INTFX RTIF WAKF INTFA INTFB IRQ/ACK Interrupt source Reset Software External (INTX) Real time interrupt Wakje-up Timer A Timer B SPI/I2C CPU interrupt RESETS SWI IRQB INT2 INT1 INT0 Vector address $FFFE - $FFFF $FFFC - $FFFD $FFFA - $FFFB $FFF8 - $FFF9 $FFF6 - $FFF7 $FFF4 - $FFF5
5
address lines:
A13 A14 A15 P02 R/W LIR CS2 CS3
- PD5 - PD6 - PD7 - PD0 - PD1 - PD4 - PD2 - PD3
control signals:
chip select signals:
The MC68HC05E0 directly provides gated chip-select and read/write signals. A complete system comprising MPU, program EPROM and RAM (optional) can thus be built without any additional circuitry. An example of this basic system is shown in Figure 5-2. The R/W signal and the chip-select signal for additional RAM (and additional I/O) is optionally available using Port D pins. CSROM is intended to select the program ROM/EPROM and is valid in the address range $3000 to $FFFF. CS2 and CS3 select address ranges $0020 to $1FFF and $2000 to $2FFF respectively. Larger, more versatile systems with more external memory and/or peripherals can be designed with the inclusion of additional chip select logic. An example of an expanded system using an MC74HC138 is shown in Figure 5-3. The gating of the chip selects with P02 (using the CS1 pin on the MC74HC138) means that the output enable pins of the EPROM(s) and RAM(s) can be grounded. If the memory's chip select is not qualified by the clock, then its output enable pin should be driven by P02 in order to avoid bus contention during the low period of P02. This type of expanded system would be useful, for example, in a development environment where several EPROM and/or RAM chips are required. Care should be taken to ensure that the loading specification of the buses is not exceeded.
MC68HC05E0
MEMORY AND ADDRESSING
MOTOROLA 5-3
CS3 (PD3) CS2 (PD2) R/W (PD1) CSROM CE R/W CE
MC68HC05E0
ROM or EPROM
(e.g. 27(C)64) OE
RAM
(optional - e.g. MCM60(L)64) OE
5
DATA ADDRESS
Figure 5-1 Minimum System with External Memory
A15 (PD7) A14 (PD6) A13 (PD5) P02 (PD0)
A2 A1 A0 CS1
MC74HC138
R/W* (PD1) CE CE CE R/W
MC68HC05E0
ROM
EPROM
RAM
OE
OE
OE
DATA ADDRESS
Figure 5-2 More Complex Expanded System
MOTOROLA 5-4
MEMORY AND ADDRESSING
MC68HC05E0
Table 5-2 Register outline
Register name Port A data register Port B data register Port C data register Port D data register Port E data register Port A data direction register Port B data direction register Port C data direction register Port D data direction register Port E data direction register Timer A prescaler register Timer B scaler register Timer control register Address bit 7 $0000 $0001 $0002 $0003 $0004 $0005 $0006 $0007 $0008 $0009 $000A $000B $000C $000D Interrupt control register SI data register PortE/SI mode register SI S register PortD mode register Wake-up enable register Wake-up phase register $000E $000F $0010 $0011 $0012 $0013 $0014 $0015 $0016 $0017 RTI control register RTI counter register $0018 $0019 TC7 RTIF TC6 TC5 RTIE TC4 TC3 TC2 RT1 TC1 RT0 TC0 0000 0011 0000 0000 WAKF INTXP INTFB INTFA INTFX INTMB INTMA INTMX 0000 0001 SD7 SIE BB EA15 WE7 WP7 SD6 SD5 SD4 WL IRQ/ ACK DM4 WE74 WP74 SD3 BD1 NMA DM3 WE3 WP3 SD2 BD0 SP DM2 WE2 WP2 SD1 PS1 ST DM1 WE1 WP1 SD0 PS0 0000 0000 0000 0000 AD7 BD7 CD7 DD7 1 AR7 BR7 CR7 DR7 1 TA7 TB7 SC1 bit 6 AD6 BD6 CD6 DD6 1 AR6 BR6 CR6 DR6 1 TA6 TB6 SC0 bit 5 AD5 BD5 CD5 DD5 1 AR5 BR5 CR5 DR5 1 TA5 TB5 PITX bit 4 AD4 BD4 CD4 DD4 1 AR4 BR4 CR4 DR4 1 TA4 TB4 PITW bit 3 AD3 BD3 CD3 DD3 ED3 AR3 BR3 CR3 DR3 ER3 TA3 TB3 1 bit 2 AD2 BD2 CD2 DD2 ED2 AR2 BR2 CR2 DR2 ER2 TA2 TB2 bit 1 AD1 BD1 CD1 DD1 ED1 AR1 BR1 CR1 DR1 ER1 TA1 TB1 bit 0 AD0 BD0 CD0 DD0 ED0 AR0 BR0 CR0 DR0 ER0 TA0 TB0 State on Reset 0000 0000 0000 0000 0000 0000 0000 0000 1111 0000 0000 0000 0000 0000 0000 0000 0000 0000 1111 0000 0000 0000 0000 0000
5
XROM CETB
CETA 0000 1100
CPHA CPOL ACK EA14 WE6 WP6 TFF/ DOIT EA13 WE5 WP5
R/WB 0000 0000 DM0 WE0 WP0 0000 0001 0000 0000 0000 0000
MC68HC05E0
MEMORY AND ADDRESSING
MOTOROLA 5-5
MC68HC05E0
$0000 Registers (32 bytes) $0020
Registers Port A data register Port B data register Port C data register Port D data register Port E data register Port A data direction register Port B data direction register Port C data direction register Port D data direction register Port E data direction register Timer A prescaler register Timer B scaler register Timer control register $00 $01 $02 $03 $04 $05 $06 $07 $08 $09 $0A $0B $0C $0D $0E $0F $10 $11 $12 $13 $14 $15 $16 $17 $18 $19 $1A $1B $1C $1D $1E $1F
$00FF $0100
Stack
Internal RAM (480 bytes)
5
$01FF $0200
External RAM (CS2) $1FFF $2000 External I/O (CS3) $2FFF $3000
Interrupt control register SI data register PortE/SI mode register SI S register Port D mode register Wake-up enable register Wake-up phase register
RTI control register RTI counter register
External ROM (CSROM)
$FFF3 $FFF4 User vectors (12 bytes) $FFFF
SPI/I2C (High byte) SPI/I2C (Low byte) Timer B (High byte) Timer B (Low byte) Timer A (High byte) Timer A (Low byte) IRQB (High byte) IRQB (Low byte) SWI (High byte) SWI (Low byte) RESET (High byte) RESET (Low byte)
$1FF4 $1FF5 $1FF6 $1FF7 $1FF8 $1FF9 $1FFA $1FFB $1FFC $1FFD $1FFE $1FFF
Figure 5-3 Memory map of the MC68HC05E0
MOTOROLA 5-6
MEMORY AND ADDRESSING
MC68HC05E0
6
PARALLEL INPUT/OUTPUT PORTS
6.1 Bidirectional Ports
6
Ports A, B, C, and D are bidirectional 8-bit ports and Port E is a 4-bit bidirectional port and may be configured as inputs or outputs under software control. The Port E lines are associated with bits 0-3 in the Port E data and data direction registers. The direction of any port line is determined by the state of the corresponding bit in the data direction register (DDR). Any port line is configured as an output if its corresponding DDR bit set to a logic one. A pin is configured as an input if its DDR bit is cleared to a logic zero. At power-on or reset, all DDRs are cleared to $00 (with the exception of DDRE which is set to $F0), which configures all I/O lines as inputs. (Note that, on reset, bit 0 of the Port D Mode register is set to one, thereby forcing Port D bit 0 to output the P02 clock signal.) All data and data direction registers can be written to and read by the CPU. Refer to Figure 6-1.
MC68HC05E0
PARALLEL INPUT/OUTPUT PORTS
MOTOROLA 6-1
Data Direction Register
MC68HC05E0 Internal Connections
Data Register
Output Buffer
I/O Pin
Input Data Reg.
Input I/O
(a)
6
Typical Port Data Direction Register Typical Port Register
DDR7 DDR6 DDR5 DDR4 DDR3 DDR2 DDR1 DDR0
I/O Port Lines
Px7
Px6
Px5
Px4
Px3
Px2
Px1
Px0
(b)
VDD Port Data Port DDR P*
PAD N*
Notes: 1. * Denotes devices have same physical size and are enhancement type. IP 2. IP = Input Protection. 3. Latch-up Protection not shown.
Internal Logic
(c)
Figure 6-1 Bidirectional I/O Port Structure
MOTOROLA 6-2
PARALLEL INPUT/OUTPUT PORTS
MC68HC05E0
6.2
Port C Wake-up Function
Each bit on Port C can be individually configured to operate in a wake-up mode which can interrupt the processor when an appropriate signal edge or level is applied to the input pin (see Figure 6-2). This is controlled by the corresponding Wake-up Enable bits (WE0 to WE7) in the Wake-up Enable Register ($0013) and Wake-up Phase bits (WP0 to WP7) in the wake-up Phase Register ($0014).
Address Wake-up enable register $0013 bit 7 WE7 bit 6 WE6 bit 5 WE5 bit 4 WE4 bit 3 WE3 bit 2 WE2 bit 1 WE1 bit 0 WE0 State on reset 0000 0000
WEx bit 1 (set) - Wake-up Interrupt enabled Wake-up Interrupt disabled
Address Wake-up phase register $0014 bit 7 WP7 bit 6 WP6 bit 5 WP5 bit 4 WP4 bit 3 WP3 bit 2 WP2 bit 1 WP1 bit 0 WP0 State on reset 0000 0000
0 (clear) -
6
WPx bit: 1 (set) - Wake-up on rising edge or logic high level Wake-up on falling edge or logic low level
0 (clear) -
PITW (program interrupt type wake-up function), bit 4 of the Timer Control Register ($000C), provides additional control of wake-up interrupts on Port C by selecting either edge or level sensitive triggering.
Address Timer control register $000C bit 7 SC1 bit 6 SC0 bit 5 PITX bit 4 PITW bit 3 1 bit 2 bit 1 bit 0 State on reset
XROM CETB
CETA 0000 1100
PITW 1 (set) - Level-triggered interrupt selected Edge-triggered only interrupt selected
0 (clear) -
If port C is used as an output port, the wake-up function is disabled. Therefore, a wake-up function can only be used in conjunction with Port C being an input (see also Timer Control Register). The wake-up function uses the INTX vector ($FFFA, $FFFB). In the INTX interrupt routine, the user should test the WAKF flag (bit 7 in the Interrupt Control Register ($000E) to see if a wake-up interrupt is pending. The wake-up interrupt routine should also clear the WAKF flag before returning to the main program flow.
MC68HC05E0
PARALLEL INPUT/OUTPUT PORTS
MOTOROLA 6-3
WAKF
6
INTX Real Time Interrupt
IRQB
8
8
Wake-up Phase Register ($0014)
Wake-up Enable Register ($0013)
Figure 6-2 Port C Wake-up Function
6.3
Port D Alternate Functions
All Port D lines can be reconfigured to provide the signals needed to interface with external memory (see Table 6-1). R/W is the Read/Write signal which is active low only during the high phase of P02 and stays high during the low phase of P02. The chip select signals CS2 and CS3 are active low and are only active during the high phase of P02. LIR is an output signal which goes low only during the first P02 clock cycle of each instruction, and remains low for the duration of that cycle. It is intended for use during debugging and emulation.
MOTOROLA 6-4
PARALLEL INPUT/OUTPUT PORTS
MC68HC05E0
Table 6-1 Port D Alternate Functions
As bidirectional I/O PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7 Alternate function P02 -- Bus frequency clock signal R/W -- Read/write signal (readwhen high, write when low) CS2 -- Chip select signal (active low) for external RAM CS3 -- Chip select signal (active low) for external I/O LIR -- Load instruction register (active low) A13 -- Address line A14 -- Address line A15 -- Address line
Pins PD5, PD6 and PD7 have internal pull-up resistors connected to VDD. Configuration of Port D is done via the Port D Mode Register ($0012).
Address Port D mode register $0012 bit 7 EA15 bit 6 EA14 bit 5 EA13 bit 4 DM4 bit 3 DM3 bit 2 DM2 bit 1 DM1 bit 0 DM0 State on reset 0000 0001
6
If a bit is set in the mode register, the corresponding port bit is used only as an output irrespective of the value in the data direction register (see Table 6-2). Figure 6-3 shows the internal structure of Port D.
Table 6-2 Port D Mode Table
Bit DM0 DM1 DM2 DM3 DM4 EA15 EA14 EA13 Value 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Function port function (bidirectional) P02 signal as output signal port function (bidirectional) RIW signal as output signal port function (bidirectional) CS2 (external RAM) signal as output signal port function (bidirectional) CS3 (external I/O) signal as output signal port function (bidirectional) LIR signal as output signal port function (bidirectional) A15 signal as output signal port function (bidirectional) A14 signal as output signal port function (bidirectional) A 13 signal as output signal
MC68HC05E0
PARALLEL INPUT/OUTPUT PORTS
MOTOROLA 6-5
VDD
MUX MUX Port D Data Register MUX MUX MUX MUX MUX MUX
PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 Port D Pads
6
($0003)
A15
A14
A13
LIR
CS3
CS2
R/W
P02
Figure 6-3 Port D Structure
6.4
Serial Interface Support Functions on Port E
Port E also supports the on-board Serial Interface (SPI and I2C functions) (see Figure 6-4). Selection of these functions is controlled via the PS0 and PS1 bits in the Port E/SI Mode Register ($0010).
Table 6-3 Port E/SI Mode Selection
PS1 0 0 1 1 PS0 0 1 0 1 Function PortE as parallel port I2C bus protocol SPI function SPI function PE0 I/O data data data PE1 I/O clock clock I/O PE2 I/O I/O I/O clock
See Section 8 for detailed information on the Serial Interface.
MOTOROLA 6-6
PARALLEL INPUT/OUTPUT PORTS
MC68HC05E0
SI Data Register ($000F)
SPI Control Logic
I 2C Control Logic E0
Selection E1 Port E Data Register ($0004) PS1 PS0 E3 E2 Logic Port E Pads
6
Figure 6-4 Port E Structure
6.5
Other Port Considerations
All ports are latched with the bus timing signal P02 (especially for inputs). All output ports can emulate open-drain outputs. This is achieved by writing a zero to the relevant output port latch. By toggling the corresponding data direction bit, the port pin will either be an output zero or tri-state (an input). Refer to Figure 6-5. When using a port pin as an open-drain output, certain precautions must be taken in the user software. If a read-modify-write instruction is used on a port where the open-drain is assigned and the pin at this time is programmed as an input, it will read it as a "one". The read-modify-write instruction will then write this "one" into the output data latch on the next cycle. This would cause the open-drain pin not to output a "zero" when desired.
Note:
"Open-drain" outputs should not be pulled above VDD.
MC68HC05E0
PARALLEL INPUT/OUTPUT PORTS
MOTOROLA 6-7
S Pad A Data Direction Register bit DDRn (a) Y
DDRn 1 1 0 (b) 0 1
A 0 1 0 1 0 1 0 1
Y 0 1 tri-state tri-state low --high high Open drain Normal operation - tri-state
6
V DD
1 0 0
VDD Px0
DDRx, Bit0 = 0 PORTx, Bit0 = 0
DDRx, Bit0 = 1 PORTx, Bit0 = 0
(c)
Figure 6-5
Port Logic Levels
MOTOROLA 6-8
PARALLEL INPUT/OUTPUT PORTS
MC68HC05E0
7
TIMERS
The MC68HC05E0 contains three timers: Timer A, Timer B and the Real Time Interrupt Timer. Timers A and B are driven by the sub-system clock, which also drives the Serial Interface sub-system. The Real Time Interrupt timer is driven from the bus clock (P02). Timer A and Timer B can generate an independent interrupt signal to the processor. Timer A has a higher interrupt priority than timer B. The Real Time Interrupt shares its interrupt vector with the External Interrupt (INTX) and the Port C Wake-up function.
7
7.1
Sub-system Clock Control
The sub-system clock frequency fsub is generated from the bus clock frequency (P02) by a selectable prescaler (see Figure 7-1).
TS (Timer Stop Gate Input Pin) Sub-system Clock Frequency
f sub
Bus Clock Frequency P02 /2 /2 /2 Timer A 00 01 10 11 MUX Timer B
SI
Timer Control Register ($000C)
SC1
SC0
CETB CETA
RTI Timer
Figure 7-1 Sub-system Clock Generation
MC68HC05E0
TIMERS
MOTOROLA 7-1
The maximum bus clock frequency (P02) is 4 MHz. One of four different sub-system clock frequencies can be selected via bits 6 and 7 (SC0 and SC1) of the Timer Control Register ($000C) (see Table 7-1).
Table 7-1 Sub-system Clock Frequency Selection
SC1 0 0 1 1 SC0 0 1 0 1 Sub-system clock frequency (fSUB) P02/8 P02/4 P02/2 P02/1
7
A Timer Stop signal on the active low TS pin allows Timer A and Timer B to be halted. TS can be used as a gate input to the two timers, thereby allowing pulse width measurement to be carried out on the input signal. Halting the timers is also useful during emulation of the device and during software debug. The SPI/I2C functions are not interrupted by the TS signal.
7.2
Timer A
Timer A consists of an 8-bit prescaler driving a 6-bit free-running counter (see Figure 7-2).
INTMA
CETA
8 Bit
6 Bit (freerunning)
OF
INT2 (16 s - 32 ms)
Sub-system Clock Frequency
Timer A Prescaler Register
$000A INTFA
Figure 7-2 Timer A Structure
MOTOROLA 7-2
TIMERS
MC68HC05E0
The Timer A Prescaler register ($000A) is an 8-bit wide data register which is used for setting the prescaler. It is a read/write register and can be loaded with any value between $00 and $FF. Writing N to this register causes the prescaler to divide by N+1. Writing to this register resets the entire timer. With the bus clock running at 4 MHz, Timer A has a range of 16 s to 32.8 ms.
7.3
Timer B
Timer B consists of a 14-bit free-running counter driving an 8-bit scaler (see Figure 7-3).
INTMB
7
CETB 14 Bit (freerunning) 8 Bit OF INT1 (32 ms - 8 s)
Sub-system Clock Frequency
$000B
Timer B Scaler Register INTFB
Figure 7-3 Timer B Structure
The Timer B Scaler Register ($000B) is an 8-bit wide data register which is used for setting the scaler. It is a read/write register and can be loaded with any value between $00 and $FF. Writing N to this register causes the scaler to divide by N+1. Writing to this register resets the entire timer. With the bus clock running at 4 MHz, this timer has a range of 32.8 ms to 8.4 s.
MC68HC05E0
TIMERS
MOTOROLA 7-3
7.4
Control Registers for Timer A and Timer B
Timer A and Timer B are enabled/disabled via the CETA (Count Enable Timer A) and CETB (Count Enable Timer B) control bits in the Timer Control Register ($000C).
Address Timer control register $000C bit 7 SC1 bit 6 SC0 bit 5 PITX bit 4 PITW bit 3 1 bit 2 bit 1 bit 0 State on reset
XROM CETB
CETA 0000 1100
CETA, CETB 1 (set) - Counter enabled Counter disabled
0 (clear) -
7
Both timers generate a signal on overflow which can be used to interrupt the processor. These signals can be masked by the INTMA and INTMB bits in the Interrupt Control Register ($000E). Timer Interrupt Flag and Acknowledge bits INTFA and INTFB indicate when a timer interrupt has occurred and can be written to reset the timer interrupt logic.
Address Interrupt control register $000C
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
State on reset
WAKF INTXP INTFB INTFA INTFX INTMB INTMA INTMX 0000 0001
INTMA, INTMB 1 (set) - Interrupts not masked Interrupts masked
0 (clear) - INTFA, INTF 1 (set) -
Interrupt has occurred Interrupt has not occurred
0 (clear) -
Writing a "0" to INTFA or INTFB acknowledges the interrupt and resets the interrupt signal for that timer.
MOTOROLA 7-4
TIMERS
MC68HC05E0
7.5
Real Time Interrupt Timer
The Real Time Interrupt circuit consists of a three stage divider and a 1 of 4 selector. The clock signal which drives the RTI circuit is P02/214 (= P02/16384) with three additional divider stages giving a maximum interrupt period of 32.8 milliseconds at a bus frequency of 4 MHz (See Figure 4-1). The 8-bit RTI Timer Counter Register ($0019) is a read only register which contains the current value of the 8-bit ripple counter at the beginning of the timer chain. Reset clears the counter. During WAIT mode the CPU clock halts but the timer remains active. If the RTIE bit is set, a timer interrupt will cause the processor to exit the WAIT mode. The timer is cleared when entering STOP mode.
RTI Counter Register ($0019) Bus Frequency P02 Divide by 4 8-bit Freerunning Counter
8
7
7-bit Counter Data Bus
RTI Select
RTI Control Register ($0018)
RTIF
RTIE
RT1
RT0 8
IRQB
Figure 7-4 Real Time Interrupt Timer Structure
MC68HC05E0
TIMERS
MOTOROLA 7-5
The RTI system is controlled via the RTI Control Register ($0018).
Address RTI control register $0018 bit 7 bit 6 RTIF bit 5 bit 4 RTIE bit 3 bit 2 bit 1 RT1 bit 0 RT0 State on reset 0000 0011
RTIF is a clearable, read-only status bit and is set when the output of the chosen selector stage (1 of 4) goes active. A CPU interrupt request will be generated (IRQB) if the Real Time Interrupt is enabled. Clearing the RTIF bit is done by writing a "zero" to it. Writing a "one" to RTIF has no effect. Reset clears RTIF. RTIF 1 (set) - RTI function has timed out and generated interrupt signal. RTI function has not timed out.
0 (clear) -
7
RTIE is a read/write control bit which allows the Real Time Interrupt to generate a CPU interrupt request (IRQ). Reset clears RTIE. RTIE 1 (set) - RTI request enabled RTI request disabled
0 (clear) -
RT1, RT0 select one of four taps from the Real Time Interrupt Select logic. On reset, these bits are set to "one" which selects the lowest periodic interrupt rate, and gives the maximum time in which to modify the bits to select a different time-out period. Care should be taken when altering RT1 and RT0 if a timeout is imminent or uncertain; if a tap is selected during a cycle in which the counter is switching, an interrupt request could be missed, or an additional one generated.
Table 7-2 Real Time Interrupt Rates (bus frequency = 4MHz)
RT1 0 0 1 1 RT0 0 1 0 1 RTI time-out period (ms) 4.1 8.2 16.4 32.8
MOTOROLA 7-6
TIMERS
MC68HC05E0
8
SERIAL INTERFACE
8.1 General
The serial interface (SI) on the MC68HC05E0 supports synchronous data transfer over one bidirectional data line and a clock line. The interface can be configured to operate as a serial peripheral interface (SPI) or as an I2C-bus interface. The microprocessor always has control of the clock signal, and is therefore always "bus master". The clock and data lines are multiplexed through port E. Port E and the serial interface lines are controlled by two serial port select bits (PS1, PS0) in the Port E/SI Mode Register ($0010.
Address Port E/SI mode register $0010 bit 7 SIE bit 6 bit 5 bit 4 WL bit 3 BD`1 bit 2 BD0 bit 1 PS1 bit 0 PS0 State on reset 0000 0000
8
CPHA CPOL
Table 8-1 PS0, PS1: Serial Port Function Selection Bits
PS1 0 0 1 1 PS0 0 1 0 1 Function Port Eas parallel port I2C bus protocol SPI function SPI function PE0 I/O data data data PE1 I/O clock clock I/O PE2 I/O I/O I/O clock
Note that bit 3 of port E is always available as a port bit. When PS0 and PS1 are set to select a serial function, the data register and direction register bits for the pins used as data and clock do not influence the state of these pins.
MC68HC05E0
SERIAL INTERFACE
MOTOROLA 8-1
The sequence of events for starting a send/receive sequence in either SPI or I2C-bus mode is as follows: 1) Write to SI Mode register ($0010). The state of bits 0 and 1 select the data and clock lines, and the protocol (see Table 8-1). 2) If sending data from the MCU to a peripheral, write the data to be sent to the SI Data register ($000F). 3) Start the send/receive sequence by writing a "1" to the DOIT bit (bit 5 in the Serial Interface Control/Status Register, the SI S Register, $0011). The SI S Register also contains control bits to determine the data direction, and whether STOP/START bits are to be added to the data (I2C-bus only). The transmission rate in SPI and I2C-bus mode is determined by BD0 and BD1 (bits 2 and 3 in the SI Mode Register) which control the division ratio applied to the subsystem clock (see Figure 8-1). The division ratios are listed in Table 8-2. Note that the maximum SI transfer rate = P02 / 6 (i.e. when SC0, SC1, BD0 and BD1 are all set to 1).
8
Sub-system Clock
/3
/2
/2
/2
/2
0
1 MUX 2
SPI / I 2 C-Clock (Baud Rate)
3
BD1 BD0
Figure 8-1 Serial Port Baud Rate Generation
Table 8-2 BD0, BD1: Serial Port Transfer Rate Selection
BD1 0 0 1 1 BD0 0 1 0 1 SI transfer rate fSUB / 48 fSUB / 24 fSUB / 12 fSUB / 6
MOTOROLA 8-2
SERIAL INTERFACE
MC68HC05E0
On completion of the transmit/receive sequence internal logic sets the IRQACK flag (bit 4 in the SI S Register) high, and an interrupt will be generated if the SIE bit (bit 7 in the SI Mode Register) was set high. In both SPI and I2C-bus mode, when the serial interface is in send mode, the data on the external data line is sampled 3 times per data bit. The majority value of the sample (the value found by at least 2 out of 3 of the samples) is compared with the expected state of data. If they are not the same, the TFF (Transmission failure) flag (bit 5 of the SI S Register) is set. This indicates that, due perhaps to noise or a hard fault such as a short circuit on the data line, the transmitted data and the actual data on the line do not match. TFF is a read-only signal. TFF is set at the end of an SPI/I2C-bus sequence.
8.2
SPI Configuration
The SPI serial interface allows data to be sent or received by the MCU over a single, bidirectional data line. An accompanying clock signal is also generated by the MCU. Four different combinations of clock phase/polarity can be generated under the control of CPOL and CPHA (bits 5 and 6 respectively in the SI Mode Register, $0010). (Refer to Figure 8-2) The clock and data pins selected by PS0 and PS1 are open-drain. External 4k7 pull-up resistors should be used. The external data line is hi-Z (pulled high by the external resistor) when the SPI is idle. The idle state of the clock line depends on the setting of CPOL/CPHA. Refer to Section 9 for more detailed information on SPI timing.
8
Idle line or preceding transmission
Start
8 Data Bits
Stop
Clock (CPOL=0, CPHA=0)
Clock (CPOL=0, CPHA=1)
Clock (CPOL=1, CPHA=0)
Clock (CPOL=1, CPHA=1)
Data Start
0 LSB
1
2
3
4
5
6
7 MSB Stop
Figure 8-2 SPI Data/Clock Relationship
MC68HC05E0
SERIAL INTERFACE
MOTOROLA 8-3
A START bit is generated on the data line before a data byte is transmitted. No START bit is generated for receive sequences. The START bit is a low state applied to the data line while the clock stays in its idle state. The START bit lasts for 1 SPI clock period (determined by BD0 and BD1 in the SI Mode Register). The SPI bus allows either 6-bit or 8-bit words to be sent or received. WL (bit 4 in SI Mode Register) determines the word length (Low = 8-bit, High = 6-bit). When a 6-bit word is to be sent, it should be written to the 6 most significant bits of the SI Data Register. After transmission, the location of the bits in the SI Data Register will have changed. The 6-bit word now resides in bits 0 to 5, and the upper 2 bits are the remaining (unused) bits. This is because the SI Data Register functions as a shift register during transmission, and the most significant bit is shifted round to the least significant bit every time a new data bit is sent. Similarly, when receiving a 6-bit word, it will be located in the lower 6 bits of SI Data Register at the end of the receive sequence. The direction of data along the data line is determined by R/WB (bit 0 in the SI S Register). R/WB = 0 sends data to a peripheral, R/WB = 1 receives data from a peripheral. The Serial Peripheral Interface is configured via the Port E/SI Mode Register ($0010).
Address bit 7 SIE bit 6 bit 5 bit 4 WL bit 3 BD`1 bit 2 BD0 bit 1 PS1 bit 0 PS0 State on reset 0000 0000
8
Port E/SI mode register
$0010
CPHA CPOL
SIE --Serial Interrupt Enable Bit This bit masks the interrupt signal generated at the end of each SPI transfer. 1 (set) - Interrupts not masked Interrupts masked
0 (clear) -
CPOL, CPHA -- Clock Polarity and Clock Phase Bits These two bits provide four possible clock polarity/phase relationships for recognition of valid data, as shown in Figure 8-2. The MC68HC05E0 SPI is always the master. The interrupt signal is generated after the last clock pulse. The START bit/STOP bit is automatically generated (only when sending). A receive sequence only clocks in the data bits sent from the slave. WL -- Word Length Bit. This bit determines whether 6-bit or 8-bit data words are to be sent/received. 1 (set) - 6-bit word length 8-bit word length
0 (clear) -
Note:
In the I2C-bus mode only 8-bit words can be transferred.
MOTOROLA 8-4
SERIAL INTERFACE
MC68HC05E0
BD1, BD0 -- Baud Rate Select Bits (see Table 8-2). PS1, PS0 -- Port Select Bits These bits should be 10 or 11 (binary) to select an SPI function (see Table 8-1). The Serial Peripheral Interface is controlled via the SI S Register ($0011).
Address Serial interface S register $0011 bit 7 BB bit 6 ACK bit 5 TFF/ DOIT bit 4 IRQ/ ACK bit 3 NMA bit 2 SP bit 1 ST bit 0 State on reset
R/WB 0000 0000
TFF/DOIT -- Transmission Failure Flag/"Do it" Bit Writing this bit high starts an SPI bus transaction. Reading this bit at the end of an SPI transmit sequence shows the state of the TFF flag. If high, this indicates a mismatch between data in the SI Data Register and the data sent on the serial data line. Writing a zero to this bit clears and resets the Transmission Failure Flag circuitry. Read 1 (set) - Transmission error No transmission error Write Start Send or Receive Clear and reset TFF
0 (clear) -
8
IRQACK -- Interrupt Acknowledge Flag Bit This bit is the serial interface interrupt flag, raised at the end of every SPI/I2C-bus transaction. Writing a zero to IRQACK clears the interrupt flag, resets the interrupt circuitry and permits new data to be written to the data register or newly received data to overwrite the old data in the reception register (meaning the data register has already been read). 1 (set) - SPI transaction completed No SPI transaction has occurred
0 (clear) -
R/WB -- Read/Write Bit This bit selects the direction of the data transfer during SPI or I2C-bus operation. 1 (set) - Read (from peripheral) Write (to peripheral)
0 (clear) -
MC68HC05E0
SERIAL INTERFACE
MOTOROLA 8-5
8.3
I2C-Bus Configuration
The I2C-bus protocol was specified by Philips. It consists of a bidirectional data line (SDA) and a bidirectional clock line (SCL). Each driver connected to the SDA and SCL lines should be open-drain. An off-chip pull-up resistor (4k7) pulls either line to a high state if the line is not being held low by an active peripheral. SDA and SCL pulled high is the I2C idle state. The original I2C-bus specification allows for different devices connected to an SDA and SCL line to be receivers, transmitters, masters (generating the SCL clock) or slaves. In the MC68HC05E0 implementation, the micro is always master. A variety of devices exist which can communicate over the I2C-bus, from complex microcontrollers (e.g. Philips 68070) to real-time clock chips, LCD drivers and "dumb" serial EEPROMs. The I2C-bus implementation on the MC68HC05E0 is intended for use in simpler bus systems, rather than complex multi-master systems. For this reason the following features of the full I2C-bus protocol are NOT supported: - - The passing of bus mastery from one peripheral to another. (The MC68HC05E0 is always bus master). Clock synchronization when two bus masters simultaneously drive SCL. Detection of data collision (2 devices sending data simultaneously). Address register and comparator to allow selection of which peripheral is to be addressed. (No I2C-bus address register is available on the MC68HC05E0)
8
- -
The I2C-bus specification calls for a pause of at least 4.7 s between the end of one transmission sequence and the start of another. This is not done in hardware by the MC68HC05E0 but, as at least three instructions are needed to load/read, set-up and start the I2C-bus circuit, the pause will always be greater than 5 s when using a 4 MHz crystal. If an 8 MHz crystal is used, software must provide a delay greater than 4.7 s. The user has control over whether START and STOP bits are generated. Also, the I2C-bus can be programmed such that the micro does or does not provide an acknowledge signal to peripherals. The I 2C-bus circuitry monitors the bus continuously to check that no other I2C-bus peripheral is currently using the bus. Figure 8-3 shows the timing relationship between the clock (SCL) and data (SDA) in I2C-bus mode. Refer to Section 9 for more detailed timing information.
MOTOROLA 8-6
SERIAL INTERFACE
MC68HC05E0
SDA
MSB
LSB
SCL
1
2
3
4
5
6
7
8
9
START
Receiver Acknowledge
STOP
Transmission of 1 Data Byte (I 2C Bus), with START and STOP - Data changes following falling edge on SCL - Data stable while SCL high
Figure 8-3 I2C-bus Data/Clock Relationship
8
A typical I2C-bus transaction starts with the MC68HC05E0 generating a START condition (SDA pulled low while SCL high). The MC68HC05E0 will then send a stream of 8 bits. The SCL line is pulsed to provide a clock waveform while data is sent. The first 7 bits of the byte specify the address of a slave peripheral, and the 8th bit specifies the direction of data between the slave and the micro - a "0" indicates write to slave, a "1" indicates read from slave. A 9th clock pulse is generated during which the addressed slave can indicate acknowledgement to the micro. This is done by the micro releasing the data line and the slave pulling the data line low. Successive bursts of 9 clock pulses are generated by the micro to synchronize transfer of data, and the receiver has the possibility to acknowledge on the 9th pulse. Data transfer is terminated by the micro generating a STOP condition (SDA goes high while SCL high). The I2C-bus Interface is configured via the SI Mode Register ($0010)
Address Port E/SI mode register $0010 bit 7 SIE bit 6 bit 5 bit 4 WL bit 3 BD`1 bit 2 BD0 bit 1 PS1 bit 0 PS0 State on reset 0000 0000
CPHA CPOL
SIE -- Serial Interrupt Enable Bit This bit masks the interrupt signal generated at the end of each I2C transfer. 1 (set) - Interrupts not masked Interrupts masked
0 (clear) -
MC68HC05E0
SERIAL INTERFACE
MOTOROLA 8-7
BD1, BD0 -- Baud Rate Select Bits (see Table 8-2). PS1, PS0 -- Port Select Bits These bits should be 01 (binary) to select an I2C-bus function (see Table 8-1). The I2C-bus Interface is controlled via the SI S Register ($0011).
Address Serial interface S register $0011 bit 7 BB bit 6 ACK bit 5 TFF/ DOIT bit 4 IRQ/ ACK bit 3 NMA bit 2 SP bit 1 ST bit 0 State on reset
R/WB 0000 0000
BB -- Bus Busy Bit BB is a read-only bit which indicates if the I2C-bus is busy or idle. BB is set if a START condition is seen on the data line. This implies that another I2C-bus master is using the bus, and that if the MC68HC05E0 tries to start an I2C-bus sequence a data/clock collision will occur. BB is cleared when the corresponding STOP condition, implying that the bus is again idle, is detected on the bus. This flag generates no interrupt.
8
1 (set)
-
Busy Idle
0 (clear) -
ACK -- Acknowledge Bit ACK is a read-only bit which goes high if an acknowledge signal is given by a peripheral (via the 9th clock bit) after the MC68HC05E0 has transmitted a byte of data to it. ACK is updated at the end of each receive sequence. 1 (set) - Acknowledgement received from peripheral Acknowledgement not received from peripheral
0 (clear) -
TFF/DOIT -- Transmission Failure Flag/"Do it" Bit Writing this bit high starts an I2C-bus transaction. Reading this bit at the end of an I2C-bus transmit sequence shows the state of the TFF flag. If high, this indicates a mismatch between data in the SI Data Register and the data sent on the serial data line. Writing a zero to this bit clears and resets the Transmission Failure Flag circuitry. Read 1 (set) - Transmission error No transmission error Write Start Send or Receive Clear and reset TFF
0 (clear) -
MOTOROLA 8-8
SERIAL INTERFACE
MC68HC05E0
IRQACK -- Interrupt Acknowledge Flag Bit This bit is the serial interface interrupt flag, raised at the end of every SPI/I2C-bus transaction. Writing a zero to IRQACK clears the interrupt flag, resets the interrupt circuitry and permits new data to be written to the data register or newly received data to overwrite the old data in the reception register (meaning the data register has already been read). 1 (set) - I2C-bus transaction completed No I2C-bus transaction has occurred
0 (clear) -
NMA -- No Master Acknowledge Bit When set high NMA prevents the MC68HC05E0 from giving an acknowledge signal to a peripheral after receiving a byte of data. An acknowledge is made if NMA is low. 1 (set) - Prevent acknowledgement after data receive Permit acknowledgement after data receive
0 (clear) - SP -- STOP Bit
If high, an I2C-bus STOP condition is generated on the SDA line at the end of the next bus transfer. If low, no STOP bit is produced. 1 (set) - Generate STOP condition after data transfer Do not generate STOP condition after data transfer
8
0 (clear) - ST -- START Bit
If high, an I2C-bus START condition is generated on the SDA line at the beginning of the next bus transfer. If low, no START bit is produced. 1 (set) - Generate START condition before data transfer Do not generate START condition before data transfer
0 (clear) -
R/WB -- Read/Write Bit This bit selects the direction of the data transfer during SPI or I2C-bus operation. 1 (set) - Read (from peripheral) Write (to peripheral)
0 (clear) -
MC68HC05E0
SERIAL INTERFACE
MOTOROLA 8-9
8.4
Transmission Error Detection
During a transmission sequence (i.e. only when sending data), the serial interface circuitry checks for transmission errors caused by external influences (e.g. picture tube arcing). This transmission error detection circuitry samples the state of the SDA output pin during transmission, using a multiple of the transmission frequency, and compares the sampled value with an expected value in an additional shadow register. The sampled values are filtered for every required value bit (i.e. a majority decision is taken). The result of the comparison is shown in the Transmission Failure Flag, TFF (bit 5 of the SI S Register, $0011) for each word transmitted. (See Figure 8-4.)
Serial Function Control
Data Register
Pad
Shadow Register
8
TFF
Comparator
Majority Calculator
Sample Logic
Sub-system Clock
Figure 8-4 Serial Interface Transmission Error Detection
MOTOROLA 8-10
SERIAL INTERFACE
MC68HC05E0
9
ELECTRICAL SPECIFICATIONS
9.1 Introduction
This section contains the electrical specifications and associated timing information for the MC68HC05E0.
9.2
Maximum Ratings
Table 9-1 Maximum ratings
9
Unit V V C C mA
This device contains protective circuitry against damage due to high static voltages or electrical fields; however, it is advised that normal precautions be taken to avoid application of any voltages higher than maximum-rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level (eg. either GND or VDD ).
Rating Supply Voltage Input Voltage Operating Temperature Range Storage Temperature Range Current Drain per Pin * Excluding V DD and V SS
Symbol VDD Vin TA Tstg ID
Value - 0.3 to 7.0 VSS - 0.3 to VDD + 0.3 TL to TH 0 to 70 - 65 to 150 25
* One pin at a time, observing maximum power dissipation limits.
MC68HC05E0
ELECTRICAL SPECIFICATIONS
MOTOROLA 9-1
9.3
Thermal Characteristics and Power Considerations
The average chip junction temperature, TJ, in degrees Celsius can be obtained from the following equation: TJ= TA + (PD * JA) Where: TA JA PD PINT PI/O = = = = = Ambient Temperature (C) Package Thermal Resistance, Junction-to-Ambient (C/W) PINT + PI/O IDD x VDD (W) = Internal Chip Power Power Dissipation on Input and Output Pins (User Determined)
Note:
For most applications PI/O < PINT and can be neglected.
An approximate relationship between PD and TJ (if PI/O is neglected) is: PD= K / (TJ + 273C) Solving the equations PD and TJ for K gives: K = PD * (TA+ 273C) + JA * PD2
9
Where K is a constant pertaining to a particular part. K can be determined by measuring PD (at equilibrium) for known TA. Using this value of K the values of PD and TJ can be obtained by solving the above equations for any value of TA. The package thermal characteristics are shown in Table 9-2. Table 9-2 Thermal Characteristics
Characteristics Thermal Resistance Plastic 68-Pin Quad Pack (PLCC)
Symbol
Value 50
Unit C/W
JA
Pins A12 - A0, PD7 - PD5, CSROM, R/W, CS2, CS3
R1 3.26 k
R2 2.38 k
C 50 pF
Test Point
R2 C R2
Figure 9-1 Equivalent Test Load
MOTOROLA 9-2
ELECTRICAL SPECIFICATIONS
MC68HC05E0
9.4
DC Electrical Characteristics
(VDD = 5.0Vdc 10%, VSS = 0 Vdc, TA = 0 to 70C) Table 9-3 DC Electrical Characteristics (5V)
Characteristic OutputVoltage ILoad =10 A ILoad = -10 A Output High Voltage (ILoad = 0.8 mA) Output Low Voltage (ILoad = 1.6 mA) Input High Voltage Input Low Voltage Supply Current (f op = 4 MHz, f osc = 8 MHz) Run Wait Stop High-Z Leakage Current (All input pins except RESET, PD5, PD6, PD7) Output High Current (V OH = 2.4 V) Port A Port B Output Low Current Port A (V OL = 0.5 V) Port A (V OL = 1.0 V) Port B (V OL = 0.5 V) Port B (V OL = 1.0 V) Input Current RESET, PD5, PD6, PD7 INTX, OSC1 Capacitance Ports (as input or output) RESET, INTX Symbol V OL V OH V OH V DD-0.8 V OL - VIH 0.7x VDD VIL VSS IDD - - - I IL - IOH - - IOL - - - - Iin -70 - C out Cin - - - - - - - 1 12 8 - - - - 8 24 4 12 mA mA mA mA A - - 10 5 mA mA - 15 12 2 - - - 10 mA mA A A - 0.2x V DD V - - V - 0.4 V - - V Min - VDD-0.1 Typ - - Max 0.1 - Unit V V
9
pF pF
Typical values at mid point of voltage range, 25C only. Wait IDD: Only timer system active. If Serial Interface active add 10% to current drain. Run IDD, Wait IDD: Measured using external square clock source (Fosc = 8 MHz), all inputs 0.2V from rail, no DC loads, maximum load on outputs 50pF (OSC2 load 20pF). Wait, Stop IDD: All ports configured as inputs, Vil = 0.2V and Vih = VDD - 0.2V. Stop IDD measured with OSC1 = VSS. Wait IDD is affected linearly by the OSC2 capacitance.
MC68HC05E0
ELECTRICAL SPECIFICATIONS
MOTOROLA 9-3
9.5
AC Electrical Characteristics
(VDD = 5.0V dc 10%, VSS = 0 Vdc, TA= 0 to 70C) Table 9-4 AC Electrical Characteristics (5V)
Characteristic Frequency of Operation Crystal External Clock Internal Operating Frequency Crystal (f osc / 2) External Clock (f osc / 2) Cycle Time Crystal Oscillator Startup Time STOP Recovery Startup Time (Crystal Oscillator) RESET Pulse Width Interrupt Pulse Width Low (Edge-Triggered) Interrupt Pulse Period Symbol fosc fosc P02 P02 tcyc tOXOV t ILCH tRL t ILIH t ILIL tOH , tOL Min - dc - dc 250 - - 1.5 125
*
Max 8.0 8.0 4.0 4.0 - 100 100 - - - -
Unit MHz MHz MHz MHz ns ms ms t cyc ns t cyc ns
9
OSC1 Pulse Width *
55
The minimum period t ILIL should not lbe less than the number of cycle times it takes to execute the interrupt service routine plus 21 t cyc.
MOTOROLA 9-4
ELECTRICAL SPECIFICATIONS
MC68HC05E0
OSC1 (1)
t RL RESET t ILIH INTX tILCH Internal Clock 4064 t cyc
Internal Address Bus
FFFE
FFFE
FFFE
FFFE
FFFF(2)
RESET or Interrupt Vector Fetch NOTES: 1. Represents the internal gating of the OSC1 pin. 2. RESET vector address shown for timing example.
Figure 9-2 Stop Recovery Timing Diagram
Table 9-5 Expanded Bus Timing
Num 1 2 3 4 5 6 7 8 9 10 11 12 Cycle Time Clock Transition Read/Write Hold Address Hold Read/ Write Delay Address Delay Data Set-up (MPU Read) Data Hold (MPU Read) Data Delay (MPU Write) Data Hold (MPU Write) Chip Select Hold Chip Select Delay Characteristic Symbol tCYC tR, t F tRWH t AH tRWD t AD tDSR tDHR tDDW tDHW tCSH tCSD Min 250 - -20 10 - - 40 -20 - 10 -20 - Typ - 10 - 20 - 40 - - 30 - - - Max DC 25 0 - 0 75 - - 50 - 0 0 Unit ns ns ns ns ns ns ns ns ns ns ns ns
9
MC68HC05E0
ELECTRICAL SPECIFICATIONS
MOTOROLA 9-5
tCYC tF P02 tR t AD t AH ADDR tF
tRWD
( tCSD )
tRWH ( tCSH )
R/W, CS2, CS3, CSROM
tDHR t DSR DATA (MPU READ)
tDDW DATA (MPU WRITE)
tDHW
9
Figure 9-3 Expanded Bus Timing Diagram
MOTOROLA 9-6
ELECTRICAL SPECIFICATIONS
MC68HC05E0
9.6
Serial Interface Timing
START Bit (Transmit only) DATA Hi-Z Idle MSB (Bit 7) MSB -1 (Bit 6)
tSTART
tVALID
CLOCK
Clock Idle Start
1st Clock
2nd Clock
tHOLD Sample Data
tHOLD Sample Data
tHOLD = 1 Bus Cycle Time + t pd tSTART = t VALID = 1/SPI Transfer Frequency
(tpd 0 30 ns) (SPI Transfer Frequency determined by BD0/BD1)
Figure 9-4 SPI Timing Diagram
9
MSB-1
SDA
MSB
tVALID
SCL
t HOLD t START
t HOLD
t HOLD = 1 Bus Cycle Time + t pd t START = t VALID = 1 / I 2C Transfer Frequency
(tpd 0 30 ns) (I2C Transfer Frequency determined by BD0/BD1)
Figure 9-5
I2C-bus Timing Diagram
MC68HC05E0
ELECTRICAL SPECIFICATIONS
MOTOROLA 9-7
THIS PAGE LEFT BLANK INTENTIONALLY
9
MOTOROLA 9-8
ELECTRICAL SPECIFICATIONS
MC68HC05E0
10
MECHANICAL DATA
10.1 68-pin PLCC Package
PD7 (A15)
PD6 (A14)
PD5 (A13)
RESET INTX
OSC1
OSC2
TEST
A11
A10
PE3
TS
A8
A9
A12
A7
9 VSS PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 VDD PB0 PB1 PB2 PB3 PB4 PB5 PB6 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26
8
7
6
5
4
3
2
1
68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 A5 A4 A3 A2 A1 A0 VDD D0 D1 D2 D3 D4 D5 D6 D7 CSROM VSS
A6
10
68-pin PLCC
52 51 50 49 48 47 46 45 44
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
PD4 (LIR)
PD0 (P02) PC7
PD1 (R/W)
PD2 (CS2)
PD3 (CS3)
Figure 10-1 Pinout for 68-pin PLCC (Plastic Leadless Chip Carrier)
PB7
PC0
PC1
PC2
MC68HC05E0
MECHANICAL DATA
PC3
PC4
PC5
PC6
PE0
PE1
PE2
MOTOROLA 10-1
THIS PAGE LEFT BLANK INTENTIONALLY
10
MOTOROLA 10-2
MECHANICAL DATA
MC68HC05E0
11
ORDERING INFORMATION
11.1 EPROMs
An 8 kbyte EPROM programmed with the customer's software (positive logic for address and data) should be submitted for pattern generation. All unused bytes should be programmed to zeroes. The EPROM should be clearly labelled, placed in a conductive IC carrier and securely packed.
11.2
Verification media
All original pattern media (EPROMs) are filed for contractual purposes and are not returned. A computer listing of the ROM code will be generated and returned along with a listing verification form. The listing should be thoroughly checked and the verification form completed, signed and returned to Motorola. The signed verification form constitutes the contractual agreement for creation of the custom mask. If desired, Motorola will program blank EPROMs (supplied by the customer) from the data file used to create the custom mask, to aid in the verification process.
11
11.3
ROM Verification Units (RVUs)
Ten MCUs containing the customer's ROM pattern will be sent for program verification. These units will have been made using the custom mask but are for the purpose of ROM verification only. For expediency, they are usually unmarked and are tested only at room temperature (25oC) and at 5 volts. These RVUs are included in the mask charge and are not production parts. They are neither backed or guaranteed by Motorola Quality Assurance. At the customer's request, an RVU wafer can be supplied. This will be shipped against the customer's initial production order.
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GLOSSARY
This section contains abbreviations and specialist words used in this data sheet and throughout the industry. Further information on many of the terms may be gleaned from Motorola's M68HC11 Reference Manual, M68HC11RM/AD, or from a variety of standard electronics text books.
$xxxx %xxxx A/D, ADC Bootstrap mode Byte CAN CCR CERQUAD Clear CMOS COP CPU D/A, DAC EEPROM EPROM
The digits following the `$' are in hexadecimal format. The digits following the `%' are in binary format. Analog-to-digital (converter). In this mode the device automatically loads its internal memory from an external source on reset and then allows this program to be executed. Eight bits. Controller area network. Condition codes register; an integral part of the CPU. A ceramic package type, principally used for EPROM and high temperature devices. `0' -- the logic zero state; the opposite of `set'. Complementary metal oxide semiconductor. A semiconductor technology chosen for its low power consumption and good noise immunity. Computer operating properly. aka `watchdog'. This circuit is used to detect device runaway and provide a means for restoring correct operation. Central processing unit. Digital-to-analog (converter). Electrically erasable programmable read only memory. aka `EEROM'. Erasable programmable read only memory. This type of memory requires exposure to ultra-violet wavelengths in order to erase previous data. aka `PROM'. Electrostatic discharge.
ESD
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Expanded mode
In this mode the internal address and data bus lines are connected to external pins. This enables the device to be used in much more complex systems, where there is a need for external memory for example. Evaluation system. One of the range of platforms provided by Motorola for evaluation and emulation of their devices. High-density complementary metal oxide semiconductor. A semiconductor technology chosen for its low power consumption and good noise immunity. Input/output; used to describe a bidirectional pin or function. (IC) This is a function provided by the timing system, whereby an external event is `captured' by storing the value of a counter at the instant the event is detected. This refers to an asynchronous external event and the handling of it by the MCU. The external event is detected by the MCU and causes a predetermined action to occur. Interrupt request. The overline indicates that this is an active-low signal format. A kilo-byte (of memory); 1024 bytes. Liquid crystal display. Least significant byte. Motorola's family of 8-bit MCUs. Microcontroller unit. Motorola interconnect bus. A single wire, medium speed serial communications protocol. Most significant byte. Half a byte; four bits. Non-return to zero. The opcode is a byte which identifies the particular instruction and operating mode to the CPU. The operand is a byte containing information the CPU needs to execute a particular instruction. (OC) This is a function provided by the timing system, whereby an external event is generated when an internal counter value matches a predefined value. Plastic leaded chip carrier package. Phase-locked loop circuit. This provides a method of frequency multiplication, to enable the use of a low frequency crystal in a high frequency circuit.
EVS HCMOS I/O Input capture
Interrupt
IRQ K byte LCD LSB M68HC05 MCU MI BUS MSB Nibble NRZ Opcode Operand Output compare
PLCC PLL
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Pull-down, pull-up These terms refer to resistors, sometimes internal to the device, which are permanently connected to either ground or VDD. PWM Pulse width modulation. This term is used to describe a technique where the width of the high and low periods of a waveform is varied, usually to enable a representation of an analog value. Quad flat pack package. Random access memory. Fast read and write, but contents are lost when the power is removed. Radio frequency interference. Real-time interrupt. Read-only memory. This type of memory is programmed during device manufacture and cannot subsequently be altered. A standard serial communications protocol. Successive approximation register. Serial communications interface. `1' -- the logic one state; the opposite of `clear'. An area in the central belt of Scotland, so called because of the concentration of semiconductor manufacturers and users found there. In this mode the device functions as a self contained unit, requiring only I/O devices to complete a system. Serial peripheral interface. This mode is intended for factory testing. Transistor-transistor logic. Universal asynchronous receiver transmitter. Voltage controlled oscillator.
QFP RAM RFI RTI ROM RS-232C SAR SCI Set Silicon glen Single chip mode SPI Test mode TTL UART VCO Watchdog Wired-OR Word XIRQ
see `COP'.
A means of connecting outputs together such that the resulting composite output state is the logical OR of the state of the individual outputs. Two bytes; 16 bits. Non-maskable interrupt request. The overline indicates that this has an active-low signal format.
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INTRODUCTION FUNCTIONAL PIN DESCRIPTION CPU CORE AND INSTRUCTION SET RESETS, INTERRUPTS AND LOW POWER MODES MEMORY AND ADDRESSING PARALLEL INPUT/OUTPUT PORTS TIMERS SERIAL INTERFACE ELECTRICAL SPECIFICATIONS MECHANICAL DATA ORDERING INFORMATION
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INTRODUCTION FUNCTIONAL PIN DESCRIPTION CPU CORE AND INSTRUCTION SET RESETS, INTERRUPTS AND LOW POWER MODES MEMORY AND ADDRESSING PARALLEL INPUT/OUTPUT PORTS TIMERS SERIAL INTERFACE ELECTRICAL SPECIFICATIONS MECHANICAL DATA ORDERING INFORMATION
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